KR100641910B1 - Method for forming metal line in semiconductor device - Google Patents

Method for forming metal line in semiconductor device Download PDF

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KR100641910B1
KR100641910B1 KR1019990067064A KR19990067064A KR100641910B1 KR 100641910 B1 KR100641910 B1 KR 100641910B1 KR 1019990067064 A KR1019990067064 A KR 1019990067064A KR 19990067064 A KR19990067064 A KR 19990067064A KR 100641910 B1 KR100641910 B1 KR 100641910B1
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layer
forming
titanium
heat treatment
cobalt
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KR20010059547A (en
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김헌도
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 콘택홀내에 Al 로 콘택플러그를 형성하여 배선의 저항을 대폭 감소시킬 수 있도록 매우 안정한 에피 코발트 실리사이드층을 콘택홀 하부에만 형성하여 반도체 소자의 제조 공정 수율을 향상시킬 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein a highly stable epi cobalt silicide layer is formed only in a lower portion of a contact hole to form a contact plug with Al in a contact hole, thereby greatly reducing wiring resistance. It is a technique that can improve the process yield.

Description

반도체 소자의 금속배선 형성방법{Method for forming metal line in semiconductor device}Method for forming metal line in semiconductor device

도 1 은 종래의 기술에 따른 금속배선 형성 상태를 도시한 단면도1 is a cross-sectional view showing a metal wiring formation state according to the prior art.

도 2a 내지 도 2d 는 본 발명이 방법에 따른 반도체 소자의 금속배선 형성공정 단계를 도시한 단면도2A to 2D are cross-sectional views showing the metallization process steps of the semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1 : 실리콘 기판 2 : 절연막  1 silicon substrate 2 insulating film

3 : 확산방지 금속층 4 : 텅스텐층 3: diffusion preventing metal layer 4: tungsten layer

5 : 반사 방지막 6 : 에피 코발트 실리사이드층 5: anti-reflection film 6: epi cobalt silicide layer

7 : 선택적 알루미늄층 8 : 제1 알루미늄 합금층 7: optional aluminum layer 8: first aluminum alloy layer

9 : 제2 알루미늄 합금층 9: second aluminum alloy layer

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 에피 코발트 실리사이드층을 콘택의 하부에 형성한 후, 선택적 알루미늄으로 제1 금속층을 형성함에 의해 배리어 금속(Barrier metal) 없이 배선을 용이하게 형성하여 반도체 소자의 동작 특성 및 제조공정 수율을 향상시킬 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In particular, an epi-cobalt silicide layer is formed under a contact, and then a wiring is easily formed without a barrier metal by forming a first metal layer of selective aluminum. The present invention relates to a method for forming a metal wiring of a semiconductor device, which can improve the operating characteristics and the manufacturing process yield of the semiconductor device.

종래의 금속배선 형성 기술에 따르면, 0.10㎛ 급 소자의 콘택 크기는 보통 0.2㎛ 이하이고, 깊이는 2.5㎛ 정도가 된다. 이때 콘택 상부의 크기는 0.2㎛ 정도로 형성 가능하지만, 콘택 하부의 경우에는 0.15㎛ 이하의 크기를 가지게 되는 등 소자의 제1 금속층 배선은 점차 어려워 지고 있다.According to the conventional metallization technology, the contact size of the 0.10㎛ class element is usually 0.2㎛ or less, the depth is about 2.5㎛. At this time, although the size of the upper portion of the contact can be formed to about 0.2 μm, the first metal layer wiring of the device becomes increasingly difficult, such as having a size of 0.15 μm or less in the case of the lower portion of the contact.

현재 제1 금속층으로 널리 사용하고 있는 텅스텐 증착의 경우도 상기의 콘택에서는 매립이 어렵고 저항이 높아 소자의 동작특성에 악 영향을 주고 있는 문제점이 있다. Tungsten deposition, which is currently widely used as a first metal layer, also has a problem in that the contact is difficult to be buried and has a high resistance, which adversely affects the operation characteristics of the device.

상기한 문제점은 콘택의 크기가 감소하지만 필요로 하는 베리어 금속의 두께는 감소하지 않아 전체 배선중 저항이 높은 배리어 금속이 차지하는 비중이 높기 때문에 전체 저항이 증가하게 되는 것이다. The problem is that the size of the contact is reduced, but the thickness of the barrier metal required is not reduced, so that the overall resistance is increased because the barrier metal having a high resistance in the entire wiring is high.

도 1 은 종래의 기술에 따른 금속배선 형성 상태를 도시한 단면도로서, 종래의 금속배선 형성공정을 고집적 소자의 콘택에 적용한 경우이다.1 is a cross-sectional view showing a metal wiring formation state according to the prior art, when the conventional metal wiring formation process is applied to the contact of the highly integrated device.

상기 도면에 도시된 바와 같이, 콘택의 내부에 대부분이 저항이 높은 베리어 금속(3)이 차지하기 때문에 소자의 동작특성에 악 영향을 미치게 된다.As shown in the figure, since the barrier metal 3 having a high resistance occupies most of the inside of the contact, it adversely affects the operation characteristics of the device.

따라서 본 발명은 상기한 종래의 문제점을 감안하여 종래의 다중 금속배선 대신 Al/TiN 만으로 금속배선을 형성하는 기술로 콘택홀내에서는 Al 만이 있어 배선저항을 대폭 줄일 수 있으며, 특히 실리콘 기판과 접촉하는 제1 금속층을 매우 안정한 에피 코발트 실리사이드층을 콘택 하부에만 형성하여 베리어 금속 없이도 순수 알루미늄만 증착 가능토록 함으로써 반도체 소자의 제조 공정 수율을 향상시킬 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Therefore, in view of the above-described problems, the present invention is a technology for forming a metal wiring using only Al / TiN instead of the conventional multi-metal wiring. In the contact hole, only Al is used, and wiring resistance can be greatly reduced. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device which can improve the yield of manufacturing process of a semiconductor device by forming a highly stable epi cobalt silicide layer only at the bottom of a contact so that only pure aluminum can be deposited without a barrier metal. .

상기 목적을 달성하기 위한 본 발명에 따른 금속배선 형성 방법은,
반도체 소자의 금속배선 형성방법에 있어서,
콘택홀이 형성된 절연막을 반도체기판 상에 형성하는 단계;
상기 콘택홀 하부의 자연산화막을 제거하는 단계;
상기 구조물 상부에 타이타늄층과 코발트층을 진공파괴 없이 순차적으로 형성하는 단계;
급속 열처리공정을 실시하여 상기 금속층을 실리사이드화 한 후, 반응하지 않은 코발트와 상부로 확산된 타이타늄층을 습식식각으로 제거하여 에피 코발트 실리사이드층을 형성하되, 상기 반응하지 않은 코발트와 상부로 확산된 타이타늄층의 제거공정은 1단계 열처리나 2단계 열처리 후 한번만 실시하거나, 1단계 및 2단계 열처리 후 각각 실시하는 단계;
상기 선택적 알루미늄 증착법을 이용하여 상기 콘택홀을 매립하는 제1 알루미늄으로 금속배선 콘택플러그를 형성하는 단계; 및
상기 실리콘과 구리를 함유하는 제2 알루미늄 합금층, 타이타늄/타이타늄 나이트라이드의 복합층 및 반사방지막의 적층구조로 상기 콘택플러그에 접속되는 금속배선을 형성하는 단계를 포함하는 것을 특징으로 한다.Metal wiring forming method according to the present invention for achieving the above object,
In the metal wiring formation method of a semiconductor element,
Forming an insulating film on which a contact hole is formed, on a semiconductor substrate;
Removing the native oxide film under the contact hole;
Sequentially forming a titanium layer and a cobalt layer on the structure without vacuum destruction;
After performing a rapid heat treatment process to silicide the metal layer, the unreacted cobalt and the diffused titanium layer were removed by wet etching to form an epi-cobalt silicide layer, but the unreacted cobalt and titanium diffused above The step of removing the layer may be performed only once after the one-step heat treatment or the two-step heat treatment, or after the first and second heat treatment, respectively;
Forming a metallization contact plug from first aluminum to fill the contact hole by using the selective aluminum deposition method; And
And forming a metal wiring connected to the contact plug in a laminated structure of the second aluminum alloy layer containing silicon and copper, a composite layer of titanium / titanium nitride, and an anti-reflection film.

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이하 첨부된 도면을 참조하여 본 발명에 대해 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d 는 본 발명의 방법에 따른 반도체 소자의 금속배선 형성 공정 단계를 도시한 단면도이다.2A through 2D are cross-sectional views illustrating metal wire forming process steps of a semiconductor device according to the method of the present invention.

상기 도 2a 는 실리콘 기판(1)에 연결되는 콘택홀을 형성하고, 상기 구조물 상에 물리 기상증착법으로 타이타늄과 코발트 층을 순차적으로 증착한 후, 1단계 혹은 2단계 열처리를 실시하여 에피 코발트 실리사이드층(6)을 형성한 다음, 반응하지 않은 코발트층과 확산하여 금속층 상부로 위치된 타이타늄층을 제거한 상태를 도시한 단면도이다.FIG. 2A illustrates a contact hole connected to the silicon substrate 1, the titanium and cobalt layers are sequentially deposited on the structure by physical vapor deposition, and then subjected to a one-step or two-step heat treatment to form an epi-cobalt silicide layer. After (6) has been formed, it is a cross-sectional view showing a state in which the titanium layer located above the metal layer is removed by diffusion with the unreacted cobalt layer.

이때 상기 콘택홀 하부에 증착되는 타이타늄층의 두께는 20∼50Å, 상기 코발트층의 증착두께는 0∼1000Å 로 한다. 그리고 상기 열처리 공정은 450∼800℃ 의 온도, N2 혹은 Ar 가스 분위기에서 1단계 또는 2단계로 급속 열처리한다.At this time, the thickness of the titanium layer deposited under the contact hole is 20 to 50 kPa, and the deposition thickness of the cobalt layer is 0 to 1000 kPa. And the heat treatment process is a rapid heat treatment in one or two stages at a temperature of 450 ~ 800 ℃, N 2 or Ar gas atmosphere.

한편, 상기 에피 코발트 실리사이드층(6)은 타이타늄 증착 전에 콘택홀 하부에 형성된 자연 산화막을 건식 혹은 습식식각 방법으로 제거한 후 진공 파괴 없이 타이타늄층을 증착하고, 열처리 후 상부로 이동된 타이타늄층과 반응하지 않은 코발트층은 습식식각 방법으로 제거함에 의해 형성되는 것이다.Meanwhile, the epi cobalt silicide layer 6 removes the natural oxide film formed under the contact hole before the deposition of titanium by dry or wet etching, and deposits the titanium layer without vacuum destruction, and does not react with the titanium layer moved upward after the heat treatment. The non-cobalt layer is formed by removing by wet etching.

이때, 특히 상기 반응하지 않은 코발트와 상부로 확산된 타이타늄층의 제거 공정은 1단계 열처리나 2단계 열처리후 실시하거나, 상기 1단계 열처리와 2단계 열처리 공정후 각각 실시한다.In this case, in particular, the step of removing the unreacted cobalt and the titanium layer diffused to the top is performed after the first step heat treatment or the second step heat treatment, or after the first step heat treatment and the second step heat treatment.

또한, 상기 콘택 하부의 자연 산화막을 제거할 시 Ar 과 H2 가스의 혼합물로 이루어진 식각가스 또는 Ar 과 He 가스 혼합물로 이루어진 식각가스를 이용하여 건식식각으로 제거한다.In addition, when removing the natural oxide layer under the contact is removed by dry etching using an etching gas consisting of a mixture of Ar and H 2 gas or an etching gas consisting of a mixture of Ar and He gas.

도 2b 는 선택적 알루미늄 증착법을 이용하여 콘택을 알루미늄(7)으로 매립한 상태를 도시한 단면도로, 콘택홀 하부의 에피 코발트 실리사이드층(6)은 보통의 코발트 실리사이드층보다 열적으로 안정하여 선택적 알루미늄 증착시에도 실리사이드층의 실리콘들이 알루미늄층으로 확산하지 않고 유지된다.FIG. 2B is a cross-sectional view showing a state in which a contact is filled with aluminum 7 using a selective aluminum deposition method, wherein the epi cobalt silicide layer 6 below the contact hole is more thermally stable than the usual cobalt silicide layer, and thus selective aluminum deposition is performed. The silicon in the silicide layer is also retained without diffusion into the aluminum layer.

도 2c 는 선택적 알루미늄층(7)을 형성한 후, 실리콘과 구리를 일정량 함유하는 제1 알루미늄 합금층(8)과 제2 알루미늄 합금층(9) 및 반자 방지층(5)을 차례로 형성한 상태를 도시한 단면도로서, 상기 알루미늄 합금층(8,9)의 형성은 알루미늄 합금 증착시 물리 기상 증착법으로 일정 고온에서 증착하여 알루미늄 합금내의 불순물 원소들이 순수 알루미늄층으로 확산해 들어가게 한다. 그리고 알루미늄 합금 증착 후 배선 신뢰성과 마스크 작업을 위해 타이타늄 나이트라이드층과 실리콘옥시나이트라이드층을 형성한다.2C shows a state in which the first aluminum alloy layer 8 containing a predetermined amount of silicon and copper, the second aluminum alloy layer 9, and the antimagnetic layer 5 are sequentially formed after the selective aluminum layer 7 is formed. As shown in the cross-sectional view, the aluminum alloy layers 8 and 9 are formed by physical vapor deposition during the deposition of aluminum alloy at a high temperature so that impurity elements in the aluminum alloy diffuse into the pure aluminum layer. After the aluminum alloy is deposited, a titanium nitride layer and a silicon oxynitride layer are formed for wiring reliability and mask operation.

상기에서 상기 알루미늄 합금층의 증착시 0.5% 미만의 실리콘과 1% 미만의 구리를 불순물로 함유된 알루미늄 합금을 300∼500℃ 의 온도에서 증착한다.When the aluminum alloy layer is deposited, an aluminum alloy containing less than 0.5% of silicon and less than 1% of copper as an impurity is deposited at a temperature of 300 to 500 ° C.

그리고 배선 신뢰성을 위해 증착되는 상기 타이타늄 나이트라이드층 대신에 타이타늄과 타이타늄 나이트라이드의 복합층으로 형성할 수도 있다.And instead of the titanium nitride layer deposited for the wiring reliability may be formed of a composite layer of titanium and titanium nitride.

도 2d 는 배선 작업을 위해 마스크 공정 및 식각 공정을 한 상태를 나타낸 단면도이다.2D is a cross-sectional view illustrating a state in which a mask process and an etching process are performed for wiring work.

한편, 상기한 본 발명은 일반적인 배선 형성방법 뿐만 아니라 다마신 패턴을 이용한 경우에도 콘택과 배선 와이어 부분에 적용한 후 화학적 기계적 연마를 통한 배선 형성을 이룰 수 있다.On the other hand, the present invention described above can be achieved by forming the wiring through the chemical mechanical polishing after applying to the contact and the wiring wire even when using a damascene pattern as well as a general wiring forming method.

또한, 향후 널리 사용되어질 메탈 패드를 이용한 경우에는 코발트층의 형성없이도 패드 금속층을 이용하여 이룰 수 있다. In addition, when using a metal pad that will be widely used in the future it can be achieved using a pad metal layer without forming a cobalt layer.

이상 상술한 바와 같은 본 발명의 방법은 실리콘 기판과 접촉하는 제1 금속층을 매우 안정한 에피 코발트 실리사이드층을 콘택홀 하부에만 형성하여 베리어 금속 없이도 순수 알루미늄만 증착 가능토록 함으로써 종래의 텅스텐 등과 같은 고 저항 금속에 의한 지연이 없어 소자 특성을 개선할 수 있으며, 에피 코발트 실리사이드층의 형성을 화학 기상 증착법으로 간단히 형성할 수 있으므로 하여 종래의 공정에 비해 경제적으로 배선을 형성할 수 있다.As described above, the method of the present invention forms a very stable epi cobalt silicide layer in contact with a silicon substrate only at the bottom of the contact hole so that only pure aluminum can be deposited without the barrier metal, thereby allowing high-resistance metals such as tungsten. Since there is no delay, the device characteristics can be improved, and since the formation of the epi cobalt silicide layer can be easily formed by chemical vapor deposition, the wiring can be formed more economically than the conventional process.

Claims (7)

반도체 소자의 금속배선 형성방법에 있어서,In the metal wiring formation method of a semiconductor element, 콘택홀이 형성된 절연막을 반도체기판 상에 형성하는 단계;Forming an insulating film on which a contact hole is formed, on a semiconductor substrate; 상기 콘택홀 하부의 자연산화막을 제거하는 단계;Removing the native oxide film under the contact hole; 상기 구조물 상부에 타이타늄층과 코발트층을 진공파괴 없이 순차적으로 형성하는 단계;Sequentially forming a titanium layer and a cobalt layer on the structure without vacuum destruction; 급속 열처리공정을 실시하여 상기 금속층을 실리사이드화 한 후, 반응하지 않은 코발트와 상부로 확산된 타이타늄층을 습식식각으로 제거하여 에피 코발트 실리사이드층을 형성하되, 상기 반응하지 않은 코발트와 상부로 확산된 타이타늄층의 제거공정은 1단계 열처리나 2단계 열처리 후 한번만 실시하거나, 1단계 및 2단계 열처리 후 각각 실시하는 단계;After performing a rapid heat treatment process to silicide the metal layer, the unreacted cobalt and the diffused titanium layer were removed by wet etching to form an epi-cobalt silicide layer, but the unreacted cobalt and titanium diffused above The step of removing the layer may be performed only once after the one-step heat treatment or the two-step heat treatment, or after the first and second heat treatment, respectively; 상기 선택적 알루미늄 증착법을 이용하여 상기 콘택홀을 매립하는 제1 알루미늄으로 금속배선 콘택플러그를 형성하는 단계; 및 Forming a metallization contact plug from first aluminum to fill the contact hole by using the selective aluminum deposition method; And 상기 실리콘과 구리를 함유하는 제2 알루미늄 합금층, 타이타늄/타이타늄 나이트라이드의 복합층 및 반사방지막의 적층구조로 상기 콘택플러그에 접속되는 금속배선을 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성방법.Forming a metal wiring connected to the contact plug in a stack structure of the second aluminum alloy layer containing silicon and copper, a composite layer of titanium / titanium nitride, and an antireflection film; . 제 1 항에 있어서The method of claim 1 상기 콘택 하부에 증착되는 타이타늄층의 두께는 20∼50Å, 상기 코발트층의 증착두께는 0∼1000Å 로 하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The thickness of the titanium layer deposited under the contact is 20 to 50 GPa, the deposition thickness of the cobalt layer is 0 to 1000 GPa. 제 1 항에 있어서The method of claim 1 상기 급속 열처리 공정은 450∼800℃ 의 온도, N2 혹은 Ar 가스 분위기에서 1단계 또는 2단계로 실시하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The rapid heat treatment process is a metal wiring forming method of a semiconductor device, characterized in that performed in one step or two steps at a temperature of 450 ~ 800 ℃, N 2 or Ar gas atmosphere. 삭제delete 제 1 항에 있어서The method of claim 1 상기 선택적 알루미늄을 증착하기 전의 단계에서 상기 콘택 하부의 자연 산화막을 제거할 시 Ar 과 H2 가스의 혼합물로 이루어진 식각가스 또는 Ar 과 He 가스 혼합물로 이루어진 식각가스를 이용하여 건식식각으로 제거하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.When removing the natural oxide layer under the contact in the step before depositing the selective aluminum, it is removed by dry etching using an etching gas consisting of a mixture of Ar and H 2 gas or an etching gas consisting of Ar and He gas mixture A metal wiring forming method of a semiconductor device. 제 1 항에 있어서The method of claim 1 상기 알루미늄 합금층의 증착시 0.5% 미만의 실리콘과 1% 미만의 구리를 불순물로 함유된 알루미늄 합금을 300∼500℃ 의 온도에서 증착하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.When the aluminum alloy layer is deposited, an aluminum alloy containing less than 0.5% silicon and less than 1% copper as an impurity is deposited at a temperature of 300 to 500 ° C. 삭제delete
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KR940016496A (en) * 1992-12-30 1994-07-23 김주용 Process for producing stable titanium-silicide (TiSi_2) via nickel or cobalt thin films
JPH10229052A (en) * 1997-02-13 1998-08-25 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPH10284439A (en) * 1997-04-08 1998-10-23 Matsushita Electron Corp Manufacture of semiconductor device
KR19990057898A (en) * 1997-12-30 1999-07-15 김영환 Method of forming barrier metal film of semiconductor device
KR20010056442A (en) * 1999-12-15 2001-07-04 박종섭 Isolation method of semiconductor devices

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940016496A (en) * 1992-12-30 1994-07-23 김주용 Process for producing stable titanium-silicide (TiSi_2) via nickel or cobalt thin films
JPH10229052A (en) * 1997-02-13 1998-08-25 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPH10284439A (en) * 1997-04-08 1998-10-23 Matsushita Electron Corp Manufacture of semiconductor device
KR19990057898A (en) * 1997-12-30 1999-07-15 김영환 Method of forming barrier metal film of semiconductor device
KR20010056442A (en) * 1999-12-15 2001-07-04 박종섭 Isolation method of semiconductor devices

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