KR100615657B1 - 격자간 원자들을 생성하기 위한 준-비정질의 경사각 주입을 이용하여 강화된 횡방향 확산을 제공하는 채널 길이가 감소된 저농도로 도핑된 드레인 트랜지스터 - Google Patents
격자간 원자들을 생성하기 위한 준-비정질의 경사각 주입을 이용하여 강화된 횡방향 확산을 제공하는 채널 길이가 감소된 저농도로 도핑된 드레인 트랜지스터 Download PDFInfo
- Publication number
- KR100615657B1 KR100615657B1 KR1020007010869A KR20007010869A KR100615657B1 KR 100615657 B1 KR100615657 B1 KR 100615657B1 KR 1020007010869 A KR1020007010869 A KR 1020007010869A KR 20007010869 A KR20007010869 A KR 20007010869A KR 100615657 B1 KR100615657 B1 KR 100615657B1
- Authority
- KR
- South Korea
- Prior art keywords
- region
- drain
- forming
- regions
- implantation
- Prior art date
Links
- 238000009792 diffusion process Methods 0.000 title claims abstract description 42
- 239000007943 implant Substances 0.000 title description 11
- 238000002513 implantation Methods 0.000 claims abstract description 74
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000001965 increasing effect Effects 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 9
- 229910052738 indium Inorganic materials 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000005728 strengthening Methods 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 description 18
- 230000000694 effects Effects 0.000 description 15
- 229910052796 boron Inorganic materials 0.000 description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 11
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000005465 channeling Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000007935 neutral effect Effects 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000011149 active material Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
EP-A-0 806 794는 반도체 기판에 얕게 도핑된 영역들을 형성하는 방법을 개시한다. 도핑 영역의 도펀트 프로파일은 실리콘 또는 게르마늄과 같은 비전기적 활성 재료의 준-비정질(sub-amorphous) 주입을 이용하여 조정된다. 상기 준-비정질 주입 에너지는 과도한 확산의 강화를 감소시키기 위해 격자간 원자(interstitial)들을 상기 접합 영역으로부터 거리를 두고 위치시키도록 선택된다.
트랜지스터 디바이스들은 오늘날 집적 회로들의 불가결한 요소들 중 하나를 구성한다. 따라서, 트랜지스터들 크기의 감소(종종 "스케일링(scaling)"이라 칭함)가 지속적으로 추구되고 있다. 종래기술인 도 1은 종래의 MOS형 트랜지스터(10)를 예시하는 부분 단면도이다. 상기 트랜지스터(10)는 기판(16) 상에 배치되는 얇은 게이트 옥사이드(14) 상부에 배치되는 도전성 게이트 영역(12)으로 이루어진다. 상기 게이트(12) 및 상기 게이트 옥사이드(14)는 기판(16)에 형성되는 드레인 영역(18)과 소스 영역(20) 간에 배치되며, 그들 사이에는 상기 게이트(12) 및 상기 게이트 옥사이드(14)의 하부 영역이 되는 채널 영역(22)이 배치된다.
Claims (11)
- 트랜지스터(50)를 형성하는 방법에 있어서,반도체 기판(56) 상에 게이트 전극(52)과 게이트 옥사이드(54)를 형성하는 단계와;드레인 영역(58)과 소스 영역(60) 중 적어도 하나에 격자간 원자들을 생성하기 위한 경사각 주입을 행함으로써 상기 게이트 옥사이드(54) 하부 위치에 기판(56)의 격자간 원자 영역들(62)을 형성하는 단계와;상기 드레인 영역(58)과 상기 소스 영역(60) 중 적어도 하나에 확장 영역(66,67)을 형성하는 단계와;상기 기판(56)의 상기 드레인 영역(58)에 드레인(70)을, 상기 소스 영역(60)에 소스(72)를 형성하는 단계와; 그리고상기 기판(56)을 열처리하는 단계를 포함하며, 여기서 상기 격자간 원자들을 생성하기 위한 경사각 주입의 주입 에너지는 상기 확장 영역(66,67)보다 실질적으로 더 얕은 격자간 원자 영역들(62)을 만들고 상기 확장 영역(66,67)의 횡방향 에지 근처에 상기 격자간 원자 영역들(62)의 격자간 원자들을 제공하도록 선택되며, 그에 의해 상기 격자간 원자 영역들(62)은 상기 확장 영역(66,67)의 수직 확산(82,86)에 실질적으로 영향을 주지 않으면서도 상기 게이트 옥사이드(54) 하부의 횡방향 확산(84)을 강화함으로써, 상기 확장 영역(66,67)의 접합 깊이를 증가시키지 않으면서도 유효 채널 길이를 감소시키는 것을 특징으로 하는 트랜지스터 형성 방법.
- 제 1 항에 있어서, 상기 경사각은 약 30-60°의 범위에 있는 것을 특징으로 하는 트랜지스터 형성 방법.
- 제 1 항에 있어서, 상기 드레인 영역(58)과 상기 소스 영역(60) 중 적어도 하나에 상기 격자간 원자들을 생성하기 위한 경사각 주입을 행하는 단계는 상기 드레인 영역(58)과 상기 소스 영역(60) 중 적어도 하나에 확장 영역(66,67)을 형성하는 단계에 선행하는 것을 특징으로 하는 트랜지스터 형성 방법.
- 제 1 항에 있어서, 상기 드레인 영역(58)과 상기 소스 영역(60) 중 적어도 하나에 상기 격자간 원자들을 생성하기 위한 경사각 주입을 행하는 단계는 실리콘, 게르마늄 또는 인듐 중 하나를 주입하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 형성 방법.
- 제 1 항에 있어서, 상기 드레인 영역(58)과 상기 소스 영역(60) 중 적어도 하나에 상기 격자간 원자들을 생성하기 위한 경사각 주입을 행하는 단계는 상기 드레인 영역(58)과 상기 소스 영역(60) 중 적어도 하나에 준-비정질 도즈를 주입하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 형성 방법.
- 제 5 항에 있어서, 상기 격자간 원자들을 생성하기 위한 경사각 주입의 도즈는 비정질화 도즈의 약 10-30%인 것을 특징으로 하는 트랜지스터 형성 방법.
- 제 1 항에 있어서, 게이트 옥사이드(54) 하부의 복합 도핑 프로파일 및 격자간 원자 프로파일은 상기 확장 영역(66,67)의 횡방향 에지(92)를 따라서는 고농도 경사를 포함하고 상기 확장 영역(66,67)의 바닥 부분(90)을 따라서는 실질적으로 더 낮은 농도 경사를 포함하며, 그로인해 상기 게이트 옥사이드(54) 하부의 강화된 횡방향 확산(84)이 얻어지는 것을 특징으로 하는 트랜지스터 형성 방법.
- 제 1 항에 있어서, 상기 드레인 영역(58)과 상기 소스 영역(60) 중 적어도 하나에 주입을 행하여 격자간 원자 영역들을 형성하는 단계 전에 상기 게이트(52) 및 상기 게이트 옥사이드(54)의 드레인 측과 소스 측 중 적어도 일측에 제 1 측벽 스페이서(100)를 형성하는 단계를 더 포함하며, 여기서 상기 제 1 측벽 스페이서(100)의 두께는 상기 게이트 옥사이드(54) 아래의 격자간 원자들의 위치를 제어함으로써 상기 트랜지스터(50)의 감소된 유효 채널 길이를 커스터마이즈하도록 허용하는 것을 특징으로 하는 트랜지스터 형성 방법.
- 제 1 항에 있어서, 상기 드레인 영역(58)과 상기 소스 영역(60) 중 적어도 하나에 상기 격자간 원자들을 생성하기 위한 경사각 주입을 행하는 단계는 쿼드 주입을 행하는 단계를 포함하는 것을 특징으로 하는 트랜지스터 형성 방법.
- 삭제
- 삭제
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/050,730 US5970353A (en) | 1998-03-30 | 1998-03-30 | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion |
US09/050,730 | 1998-03-30 | ||
US9/050,730 | 1998-03-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010042320A KR20010042320A (ko) | 2001-05-25 |
KR100615657B1 true KR100615657B1 (ko) | 2006-08-25 |
Family
ID=21967049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020007010869A KR100615657B1 (ko) | 1998-03-30 | 1998-11-24 | 격자간 원자들을 생성하기 위한 준-비정질의 경사각 주입을 이용하여 강화된 횡방향 확산을 제공하는 채널 길이가 감소된 저농도로 도핑된 드레인 트랜지스터 |
Country Status (5)
Country | Link |
---|---|
US (2) | US5970353A (ko) |
EP (1) | EP1068637A1 (ko) |
JP (1) | JP4708563B2 (ko) |
KR (1) | KR100615657B1 (ko) |
WO (1) | WO1999050900A1 (ko) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5645440A (en) | 1995-10-16 | 1997-07-08 | Masimo Corporation | Patient cable connector |
US6541756B2 (en) | 1991-03-21 | 2003-04-01 | Masimo Corporation | Shielded optical probe having an electrical connector |
JPH11168069A (ja) * | 1997-12-03 | 1999-06-22 | Nec Corp | 半導体装置の製造方法 |
US6048784A (en) * | 1997-12-17 | 2000-04-11 | Texas Instruments Incorporated | Transistor having an improved salicided gate and method of construction |
US6153455A (en) | 1998-10-13 | 2000-11-28 | Advanced Micro Devices | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
US6174778B1 (en) * | 1998-12-15 | 2001-01-16 | United Microelectronics Corp. | Method of fabricating metal oxide semiconductor |
KR100289810B1 (ko) * | 1999-05-10 | 2001-05-15 | 김영환 | 반도체 소자 제조를 위한 할로 이온 주입 방법 |
US6194293B1 (en) * | 1999-05-25 | 2001-02-27 | Advanced Micro Devices, Inc. | Channel formation after source and drain regions are formed |
FR2794898B1 (fr) * | 1999-06-11 | 2001-09-14 | France Telecom | Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication |
US6194278B1 (en) * | 1999-06-21 | 2001-02-27 | Infineon Technologies North America Corp. | Device performance by employing an improved method for forming halo implants |
US7091093B1 (en) * | 1999-09-17 | 2006-08-15 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a semiconductor device having a pocket dopant diffused layer |
US6319798B1 (en) * | 1999-09-23 | 2001-11-20 | Advanced Micro Devices, Inc. | Method for reducing lateral dopant gradient in source/drain extension of MOSFET |
US7192836B1 (en) * | 1999-11-29 | 2007-03-20 | Advanced Micro Devices, Inc. | Method and system for providing halo implant to a semiconductor device with minimal impact to the junction capacitance |
US6255175B1 (en) * | 2000-01-07 | 2001-07-03 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with minimized parasitic Miller capacitance |
US20020061309A1 (en) * | 2000-03-08 | 2002-05-23 | Garger Stephen J. | Production of peptides in plants as N-terminal viral coat protein fusions |
US6500739B1 (en) * | 2001-06-14 | 2002-12-31 | Taiwan Semiconductor Manufacturing Company | Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect |
US6475885B1 (en) * | 2001-06-29 | 2002-11-05 | Advanced Micro Devices, Inc. | Source/drain formation with sub-amorphizing implantation |
US6489223B1 (en) | 2001-07-03 | 2002-12-03 | International Business Machines Corporation | Angled implant process |
US6649460B2 (en) | 2001-10-25 | 2003-11-18 | International Business Machines Corporation | Fabricating a substantially self-aligned MOSFET |
US6509221B1 (en) | 2001-11-15 | 2003-01-21 | International Business Machines Corporation | Method for forming high performance CMOS devices with elevated sidewall spacers |
KR100422326B1 (ko) * | 2002-06-25 | 2004-03-11 | 동부전자 주식회사 | 반도체 소자의 제조방법 |
DE10261374B4 (de) * | 2002-12-30 | 2010-01-21 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung von als Feldeffekttransistor ausgebildeten Halbleiterelementen mit verbesserten Dotierprofilen |
US20040124458A1 (en) * | 2002-12-31 | 2004-07-01 | Chandrasekharan Kothandaraman | Programmable fuse device |
US6927414B2 (en) * | 2003-06-17 | 2005-08-09 | International Business Machines Corporation | High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof |
EP1678750A1 (en) * | 2003-10-17 | 2006-07-12 | Koninklijke Philips Electronics N.V. | Semiconductor device and method of manufacturing such a semiconductor device |
US7118979B2 (en) * | 2003-11-05 | 2006-10-10 | Texas Instruments Incorporated | Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode |
CN1694263A (zh) * | 2004-05-07 | 2005-11-09 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
KR100698069B1 (ko) * | 2004-07-01 | 2007-03-23 | 동부일렉트로닉스 주식회사 | 씨모스 이미지 센서의 제조방법 |
US7122435B2 (en) * | 2004-08-02 | 2006-10-17 | Texas Instruments Incorporated | Methods, systems and structures for forming improved transistors |
DE102004042156B4 (de) * | 2004-08-31 | 2010-10-28 | Advanced Micro Devices, Inc., Sunnyvale | Transistor mit asymmetrischem Source/Drain- und Halo- Implantationsgebiet und Verfahren zum Herstellen desselben |
US10188348B2 (en) | 2006-06-05 | 2019-01-29 | Masimo Corporation | Parameter upgrade system |
US7880626B2 (en) | 2006-10-12 | 2011-02-01 | Masimo Corporation | System and method for monitoring the life of a physiological sensor |
JP2008198763A (ja) * | 2007-02-13 | 2008-08-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2008085355A (ja) * | 2007-10-22 | 2008-04-10 | Toshiba Corp | イオン注入方法 |
DE102008026213B3 (de) * | 2008-05-30 | 2009-09-24 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Durchlassstromerhöhung in Transistoren durch asymmetrische Amorphisierungsimplantation |
US8372735B2 (en) * | 2008-08-14 | 2013-02-12 | Varian Semiconductor Equipment Associates, Inc. | USJ techniques with helium-treated substrates |
US8124506B2 (en) * | 2008-08-14 | 2012-02-28 | Varian Semiconductor Equipment Associates, Inc. | USJ techniques with helium-treated substrates |
US8571619B2 (en) | 2009-05-20 | 2013-10-29 | Masimo Corporation | Hemoglobin display and patient treatment |
JP6723775B2 (ja) * | 2016-03-16 | 2020-07-15 | エイブリック株式会社 | 半導体装置および半導体装置の製造方法 |
WO2018125074A1 (en) * | 2016-12-28 | 2018-07-05 | Intel Corporation | Asymmetric transistors and related devices and methods |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
PL141094B1 (en) * | 1983-12-09 | 1987-06-30 | Polska Akad Nauk Centrum | Microwave balun transformer,especially for mixers and modulators |
US4746964A (en) * | 1986-08-28 | 1988-05-24 | Fairchild Semiconductor Corporation | Modification of properties of p-type dopants with other p-type dopants |
US4861729A (en) * | 1987-08-24 | 1989-08-29 | Matsushita Electric Industrial Co., Ltd. | Method of doping impurities into sidewall of trench by use of plasma source |
JP3104265B2 (ja) * | 1990-05-30 | 2000-10-30 | 松下電器産業株式会社 | イオン注入方法 |
US5091763A (en) * | 1990-12-19 | 1992-02-25 | Intel Corporation | Self-aligned overlap MOSFET and method of fabrication |
US5362982A (en) * | 1992-04-03 | 1994-11-08 | Matsushita Electric Industrial Co., Ltd. | Insulated gate FET with a particular LDD structure |
JPH0629527A (ja) * | 1992-07-10 | 1994-02-04 | Asahi Kasei Micro Syst Kk | 半導体装置およびその製造方法 |
JPH06267974A (ja) * | 1993-03-12 | 1994-09-22 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
US5500379A (en) * | 1993-06-25 | 1996-03-19 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing semiconductor device |
US5308780A (en) * | 1993-07-22 | 1994-05-03 | United Microelectronics Corporation | Surface counter-doped N-LDD for high hot carrier reliability |
US5360749A (en) * | 1993-12-10 | 1994-11-01 | Advanced Micro Devices, Inc. | Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold current near the substrate surface |
US5470794A (en) * | 1994-02-23 | 1995-11-28 | Advanced Micro Devices | Method for forming a silicide using ion beam mixing |
JPH07263682A (ja) * | 1994-03-24 | 1995-10-13 | Oki Electric Ind Co Ltd | サリサイド構造を有するmosfetの製造方法 |
US5574685A (en) * | 1994-09-01 | 1996-11-12 | Advanced Micro Devices, Inc. | Self-aligned buried channel/junction stacked gate flash memory cell |
US5593907A (en) * | 1995-03-08 | 1997-01-14 | Advanced Micro Devices | Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices |
JPH08250728A (ja) * | 1995-03-10 | 1996-09-27 | Sony Corp | 電界効果型半導体装置及びその製造方法 |
JP2848439B2 (ja) * | 1995-11-10 | 1999-01-20 | 日本電気株式会社 | 半導体装置の製造方法 |
US5719425A (en) * | 1996-01-31 | 1998-02-17 | Micron Technology, Inc. | Multiple implant lightly doped drain (MILDD) field effect transistor |
US5627087A (en) * | 1996-03-11 | 1997-05-06 | United Microelectronics Corporation | Process for fabricating metal-oxide semiconductor (MOS) transistors based on lightly doped drain (LDD) structure |
KR970072066A (ko) * | 1996-04-29 | 1997-11-07 | 윌리엄 비. 켐플러 | 보다 얕은 접합을 이루기 위하여 도펀트 주입에 앞서 사용되는 서브-비정질화 드레시홀드량 주입 에너지를 최적화하는 방법 |
US5654215A (en) * | 1996-09-13 | 1997-08-05 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
US5747373A (en) * | 1996-09-24 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Nitride-oxide sidewall spacer for salicide formation |
US5847428A (en) * | 1996-12-06 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit gate conductor which uses layered spacers to produce a graded junction |
US6124610A (en) * | 1998-06-26 | 2000-09-26 | Advanced Micro Devices, Inc. | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
US6268640B1 (en) * | 1999-08-12 | 2001-07-31 | International Business Machines Corporation | Forming steep lateral doping distribution at source/drain junctions |
-
1998
- 1998-03-30 US US09/050,730 patent/US5970353A/en not_active Expired - Lifetime
- 1998-11-24 WO PCT/US1998/024907 patent/WO1999050900A1/en active IP Right Grant
- 1998-11-24 EP EP98960360A patent/EP1068637A1/en not_active Withdrawn
- 1998-11-24 JP JP2000541729A patent/JP4708563B2/ja not_active Expired - Fee Related
- 1998-11-24 KR KR1020007010869A patent/KR100615657B1/ko not_active IP Right Cessation
-
1999
- 1999-09-20 US US09/400,524 patent/US6593623B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5970353A (en) | 1999-10-19 |
JP4708563B2 (ja) | 2011-06-22 |
US6593623B1 (en) | 2003-07-15 |
EP1068637A1 (en) | 2001-01-17 |
WO1999050900A1 (en) | 1999-10-07 |
KR20010042320A (ko) | 2001-05-25 |
JP2002510861A (ja) | 2002-04-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100615657B1 (ko) | 격자간 원자들을 생성하기 위한 준-비정질의 경사각 주입을 이용하여 강화된 횡방향 확산을 제공하는 채널 길이가 감소된 저농도로 도핑된 드레인 트랜지스터 | |
US6008099A (en) | Fabrication process employing a single dopant implant for formation of a drain extension region and a drain region of an LDD MOSFET using enhanced lateral diffusion | |
US6682980B2 (en) | Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant | |
KR100535953B1 (ko) | N 채널 트랜지스터 및 p 채널 트랜지스터의 성능을 독립적으로 최적화하기 위해 제거가능한 측벽 스페이서를 이용하는 cmos 제조 방법 | |
US7217627B2 (en) | Semiconductor devices having diffusion barrier regions and halo implant regions and methods of fabricating the same | |
US8187959B2 (en) | Semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same | |
KR100954874B1 (ko) | 채널 영역에서 레트로그레이드 도펀트 프로필을 구비한반도체 디바이스 및 그 제조 방법 | |
JP4597531B2 (ja) | チャネル領域のドーパント分布がレトログレードな半導体デバイスおよびそのような半導体デバイスの製造方法 | |
JP5437112B2 (ja) | 金属酸化物半導体デバイスのゲート電極を形成する方法及び金属酸化物半導体デバイスを形成する方法 | |
US5536959A (en) | Self-aligned charge screen (SACS) field effect transistors and methods | |
US5976956A (en) | Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device | |
US4912053A (en) | Ion implanted JFET with self-aligned source and drain | |
JP4260905B2 (ja) | 集積回路を製造するための方法 | |
JPH10125920A (ja) | Mosトランジスタおよびその形成方法 | |
JPH05218081A (ja) | 浅い半導体接合の形成方法 | |
US20050136623A1 (en) | Shallow amorphizing implant for gettering of deep secondary end of range defects | |
KR100732630B1 (ko) | 불순물 도핑 영역을 포함하는 반도체 소자 및 그 형성 방법 | |
KR100574172B1 (ko) | 반도체 소자의 제조방법 | |
KR20020025892A (ko) | 반도체 디바이스 제조 방법 | |
US6180470B1 (en) | FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements | |
US7022577B2 (en) | Method of forming ultra shallow junctions | |
US6188106B1 (en) | MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties | |
KR100549575B1 (ko) | 반도체장치의 pmos트랜지스터 제조 방법 | |
US5930592A (en) | Asymmetrical n-channel transistor having LDD implant only in the drain region | |
KR20010051564A (ko) | Cmos 기술의 rta로 채널 하부에 할로 주입 영역을생성하는 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20120727 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20130723 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20140722 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20150717 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20160720 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20170719 Year of fee payment: 12 |
|
LAPS | Lapse due to unpaid annual fee |