KR100612542B1 - Method of forming a copper wiring in a semiconductor device - Google Patents

Method of forming a copper wiring in a semiconductor device Download PDF

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KR100612542B1
KR100612542B1 KR1020000032922A KR20000032922A KR100612542B1 KR 100612542 B1 KR100612542 B1 KR 100612542B1 KR 1020000032922 A KR1020000032922 A KR 1020000032922A KR 20000032922 A KR20000032922 A KR 20000032922A KR 100612542 B1 KR100612542 B1 KR 100612542B1
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copper
semiconductor device
copper wiring
forming
layer
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KR20010112965A (en
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표성규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 구리배선 형성방법에 관한 것으로, 구리를 금속배선으로 사용하는 기술에서 소자가 초 미세구조로 되어감에 따라 절연막에 형성된 이중 다마신 패턴 내부로의 구리매립 한계를 극복하기 위하여 이중 다마신 패턴 측벽에 시드층 스페이서를 형성하고, 시드층 스페이서 표면에 화학적 강화제층을 형성한 후 구리전구체를 이용한 MOCVD법으로 선택적 성장에 의해 구리를 성장시켜 구리배선을 형성하므로써 미세한 구조에서도 신뢰성이 우수한 구리배선을 용이하게 형성할 수 있는 반도체 소자의 구리배선 형성방법이 개시된다.
The present invention relates to a method for forming a copper wiring of a semiconductor device, in order to overcome the limitations of the embedding of copper into the double damascene pattern formed in the insulating film as the device becomes an ultra-fine structure in the technique using copper as a metal wiring A seed layer spacer is formed on the sidewall of the damascene pattern, and a chemical reinforcing layer is formed on the seed layer spacer surface, and then copper is formed by growing copper by selective growth by MOCVD method using a copper precursor. Disclosed is a method for forming a copper wiring of a semiconductor device which can easily form excellent copper wiring.

구리배선, 시드층, 화학적 강화제층, 유기금속 화학기상증착, 구리 전구체Copper wiring, seed layer, chemical enhancer layer, organometallic chemical vapor deposition, copper precursor

Description

반도체 소자의 구리배선 형성방법{Method of forming a copper wiring in a semiconductor device} Method of forming a copper wiring in a semiconductor device             

도 1a 내지 1f는 본 발명에 따른 반도체 소자의 구리배선 형성방법을 설명하기 위해 순차적으로 도시한 단면도.
1A to 1F are cross-sectional views sequentially illustrating a method of forming a copper wiring of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

10 : 반도체 기판 11 : 제 1 절연막10 semiconductor substrate 11 first insulating film

12 : 제 1 금속층 13 : 층간 절연막12 first metal layer 13 interlayer insulating film

14 : 확산 방지막 15 : 시드층14 diffusion barrier 15 seed layer

15a : 시드층 스페이서 16 : 화학적 강화제층15a: seed layer spacer 16: chemical reinforcing layer

17 : 구리 17a : 구리배선
17 copper 17a copper wiring

본 발명은 구리를 이용하여 금속배선을 형성하는 반도체 소자의 구리배선 형 성방법에 관한 것이다.
The present invention relates to a method for forming a copper wiring of a semiconductor device to form a metal wiring using copper.

현재 금속배선 재료로서 알루미늄을 이용하고 있으나, 차세대 반도체 소자의 급격한 고성능화 추세로 인하여 콘택의 크기가 감소하게 되고, 단차(Aspect ratio)가 급격하게 증가하게 되어 알루미늄을 이용한 금속배선은 한계가 있다. 이렇게 반도체 소자의 집적도가 증가하고, 이에 의해 신호전달 속도가 빨라져야함에 따라 전류를 전달하여 주는 금속 배선으로서 기존의 알루미늄 대신 비저항이 약 40% 낮은 구리를 사용하려는 연구가 진행중이다. 구리를 금속 배선으로 사용하기 위한 방법으로 생산비용 측면 및 증착속도 면에서 유리한 전기도금법(Electroplating)을 상용화하는 것이 진행되고있다. 그러나 전기도금법도 초미세구조에서는 매립에 한계가 일어날 것이기 때문에 화학 기상 증착(CVD)법을 이용한 구리증착이 차세대에서는 필연적으로 대두될 것이다. 또한, 구리의 직접적인 식각은 용이하지 않기 때문에 구리 배선이 형성될 부분에 이중 다마신 패턴을 미리 형성한 후 구리를 매립하고 화학적 기계적 연마공정을 실시하므로써 구리배선을 형성하는 방법이 일반적이다.Although aluminum is currently used as a metal wiring material, the size of a contact is reduced due to the rapid increase in performance of next-generation semiconductor devices, and the aspect ratio is sharply increased, so the metal wiring using aluminum is limited. As the degree of integration of semiconductor devices increases and signal transmission speeds increase, studies are underway to use copper having a specific resistance of about 40% lower than that of aluminum as a metal wiring for transferring current. As a method for using copper as metal wiring, commercialization of electroplating, which is advantageous in terms of production cost and deposition rate, is progressing. However, the electroplating method will be limited in the landfill in the ultra-fine structure, copper deposition using chemical vapor deposition (CVD) will inevitably emerge in the next generation. In addition, since the direct etching of copper is not easy, a method of forming copper wiring by forming a double damascene pattern in advance in the portion where the copper wiring is to be formed and then embedding copper and performing a chemical mechanical polishing process is common.

이러한 이중 다마신 패턴에 구리를 매립하여 구리 배선을 형성하는 방법을 개략적으로 설명하면 다음과 같다.A method of forming a copper wiring by embedding copper in the double damascene pattern will be described as follows.

반도체 소자를 제조하기 위한 다수의 구조가 형성된 반도체 기판 상부에 형성된 층간 절연막의 소정 영역을 패터닝하여 이중 다마신 패턴을 형성한 후 반도체 기판의 표면에 형성된 자연 산화막을 진공상태에서 스퍼터 세정 공정으로 제거한 다. 그리고, 이중 다마신 패턴을 포함한 층간 절연막 표면에 확산 방지막을 형성한다. 이후 이중 다마신 패턴 내부로 구리를 매립하고, 화학적 기계적 연마공정을 실시하여 배선을 위한 이중 다마신 패턴 내부의 구리를 제외한 층간 절연막 표면의 구리 및 확산 방지막을 제거한다.After forming a double damascene pattern by patterning a predetermined region of an interlayer insulating film formed on the semiconductor substrate having a plurality of structures for manufacturing a semiconductor device, the natural oxide film formed on the surface of the semiconductor substrate is removed by a sputter cleaning process in a vacuum state. . Then, a diffusion barrier film is formed on the surface of the interlayer insulating film including the double damascene pattern. Thereafter, copper is embedded into the double damascene pattern and a chemical mechanical polishing process is performed to remove the copper and the diffusion barrier layer on the interlayer insulation layer except for the copper inside the double damascene pattern.

그러나 상기한 바와 같은 화학적 기상 증착법을 이용한 구리배선 형성방법은 낮은 증착속도 및 높은 생산비용으로 인하여 이의 개발에 어려움이 따르고 있어서 벌크 필링(Bulk filling)에는 한계가 있다.
However, the copper wiring formation method using the chemical vapor deposition method as described above is difficult to develop due to the low deposition rate and high production cost, there is a limitation in the bulk filling (Bulk filling).

따라서, 본 발명은 시드층 스페이서를 형성하고 CECVD 공정으로 화학적 강화제를 형성한 후 구리전구체를 이용한 MOCVD 공정으로 구리를 증착하여 구리배선을 형성하므로써 미세한 구조에서도 신뢰성이 우수한 구리배선을 형성할 수 있는 반도체 소자의 구리배선 형성방법이 개시된다.
Accordingly, the present invention forms a seed layer spacer, a chemical reinforcing agent is formed by a CECVD process, and then deposits copper by a MOCVD process using a copper precursor to form a copper wiring, thereby forming a highly reliable copper wiring in a fine structure. Disclosed is a method for forming a copper wiring of an element.

이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 구리 배선 형성 방법은 반도체 소자를 형성하기 위한 여러 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하고, 상기 층간 절연막의 소정 영역을 패터닝하여 다마신 패턴을 형성하는 단계; 상기 다마신 패턴을 포함한 층간 절연막 상부에 확산 방지막을 형성하는 단계; 상기 확산방지막 상에 시드층을 형성한 후, 전면식각 공정을 실시하여 시드층 스페이서를 형성하는 단계; 상기 시드층 스페이서 측벽에만 화학적 강화제층 을 형성하는 단계; 상기 다마신 패턴이 매립되도록 전체 구조 상부에 구리층을 형성하는 단계; 수소환원 열처리 공정 후 화학적 기계적 연마 공정을 실시하여 구리배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.
In order to achieve the above object, a copper wiring forming method of a semiconductor device of the present invention forms an interlayer insulating film on a semiconductor substrate having various structures for forming a semiconductor device, and patterns a predetermined region of the interlayer insulating film to form a damascene pattern. Forming; Forming a diffusion barrier over the interlayer insulating layer including the damascene pattern; Forming a seed layer spacer by forming a seed layer on the diffusion barrier layer and then performing an entire surface etching process; Forming a chemical enhancer layer only on the seed layer spacer sidewalls; Forming a copper layer on the entire structure to fill the damascene pattern; And performing a chemical mechanical polishing process after the hydrogen reduction heat treatment process to form a copper wiring.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a를 참조하면, 반도체 소자를 제조하기 위한 여러 구조가 형성된 반도체 기판(10) 상에 제 1 절연막(11), 제 1 금속층(12) 및 층간 절연막(13)을 순차적으로 형성한 후, 층간 절연막(13)에 콘택홀 및 트랜치로 이루어진 다마신 패턴을 형성하고 세정 공정을 실시한다. 다마신 패턴의 측벽을 포함한 층간 절연막(13)의 표면에 확산 방지막(14)을 형성한다.Referring to FIG. 1A, a first insulating film 11, a first metal layer 12, and an interlayer insulating film 13 are sequentially formed on a semiconductor substrate 10 on which various structures for manufacturing a semiconductor device are formed, and then interlayers are formed. A damascene pattern made of a contact hole and a trench is formed in the insulating film 13 and a cleaning process is performed. A diffusion barrier film 14 is formed on the surface of the interlayer insulating film 13 including sidewalls of the damascene pattern.

층간 절연막(13)은 저유전상수값을 가지는 절연물질을 이용하여 형성한다. 층간 절연막(13)에 형성된 다마신 패턴은 듀얼 다마신 방식으로 형성된다. 세정 공정은 제 1 금속층(12)이 W 및 Al등의 금속일 경우에는 RF 플라즈마를 이용한다. 제 1 금속층(12)이 Cu일 경우에는 리액티브 세정(reactive cleaning) 방법을 적용하여 실시한다. 확산 방지막(14)은 ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN, CVD TiAlN, CVD TiSiN, CVD TaSiN 중 적어도 어느 하나로 형성한다.The interlayer insulating film 13 is formed using an insulating material having a low dielectric constant value. The damascene pattern formed on the interlayer insulating film 13 is formed in a dual damascene manner. The cleaning process uses RF plasma when the first metal layer 12 is metal such as W and Al. When the first metal layer 12 is Cu, a reactive cleaning method is applied. The diffusion barrier 14 is formed of at least one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN, CVD TiAlN, CVD TiSiN, and CVD TaSiN.

도 1b를 참조하면, 시드층(15)을 확산 방지막(14) 상부에 형성한다. Referring to FIG. 1B, the seed layer 15 is formed on the diffusion barrier 14.

시드층(15)은 50 내지 500Å의 두께로 Cu, Ti 및 Al 중 어느 하나를 이용하 여 형성한다. 시드층(15)은 상기한 전도체 금속대신에 화학적 강화제(Chemical Enhancer)가 잘 부착될 수 있는 부도체로도 형성할 수 있다. The seed layer 15 is formed using any one of Cu, Ti, and Al with a thickness of 50 to 500 kPa. The seed layer 15 may be formed of an insulator in which a chemical enhancer may be attached to the conductive metal instead of the conductive metal.

도 1c를 참조하면, 전면 식각공정으로 시드층(15)이 이중 다마신 패턴의 측벽에만 남도록 식각하여 시드층 스페이서(15a)를 형성한다.Referring to FIG. 1C, the seed layer 15 is etched so that the seed layer 15 remains only on sidewalls of the dual damascene pattern through a front surface etching process to form the seed layer spacer 15a.

도 1d를 참조하면, 시드층 스페이서(15a)를 포함한 전체구조상에 화학적 강화제층(16)을 형성한다. Referring to FIG. 1D, the chemical reinforcement layer 16 is formed on the entire structure including the seed layer spacer 15a.

화학적 강화제층(16)은 시드층에 선택성이 좋기 때문에 시드층 스페이서(15a)에 집중적으로 생기게 되어 스페이서 형태로 형성된다. 화학적 강화제층(16)은 I(요오드)함유 액체화합물, Hhfac1/2H2O, Hhfac, TMVS 순수(pure) I2, I(요오드) 함유 가스 및 수증기(water vapor)중 어느 하나를 촉매로 이용하여 CECVD(Chemically Enhanced CVD)공정으로 형성한다. 또한 주기율표상의 7족 원소들인 액체상태의 F, Cl, Br, I, Ar, 가스상태의 F, Cl, Br, I, Ar도 촉매로 사용된다. CECVD 공정 시간은 촉매 및 그 화합물을 액체 및 가스 상태의 운송이 가능한 리퀴드 딜리버리 시스템(LDS)이 포함된 유기금속 화학기상증착(MOCVD) 장비에서 1 내지 600초 동안 실시된다. CECVD 공정은 -20 내지 300℃에서 실시되기 때문에 유기금속 화학기상증착(MOCVD) 장비 역시 -20 내지 300℃의 온도에서 공정이 가능해야 한다.Since the chemical enhancer layer 16 has good selectivity to the seed layer, the chemical reinforcing layer 16 is concentrated in the seed layer spacer 15a to form a spacer. The chemical reinforcing layer 16 uses any one of I (iodine) -containing liquid compounds, Hhfac 1/2 H 2 O, Hhfac, TMVS pure I 2, I (iodine) containing gas, and water vapor as catalysts. It is formed by a CECVD (Chemically Enhanced CVD) process. In addition, the Group 7 elements of the periodic table, liquid F, Cl, Br, I, Ar, and gaseous F, Cl, Br, I, Ar are also used as catalysts. CECVD process times are carried out for 1 to 600 seconds in organometallic chemical vapor deposition (MOCVD) equipment that includes a liquid delivery system (LDS) capable of transporting the catalyst and its compounds in liquid and gaseous state. Since the CECVD process is carried out at -20 to 300 ℃, organometallic chemical vapor deposition (MOCVD) equipment must also be capable of processing at a temperature of -20 to 300 ℃.

도 1e를 참조하면, 유기금속 화학기상증착법(MOCVD)으로 이중 다마신 패턴내부를 구리(Cu)로 매립한다. 이러한 공정은 도 1d의 공정에서 사용된 요오드등의 화 학적 강화제가 집중되어 있는 부분을 중심으로 구리(Cu)의 증착이 가속화되기 때문에 이중 다마신 패턴 내부가 구리(Cu)로 쉽게 매립된다. 구리의 매립은 (hfac)CuVTMOS 계열, (hfac)CuDMB 계열 및 (hfac)CuTMVS 계열 등의 hfac를 이용한 모든 종류의 구리 전구체를 이용하여 다이렉트 리퀴드 인젝션(DLI), 컨트롤 에바퍼레이션 믹서(CEM), 오리피스(orifice) 방식 및 스프레이(spray) 방식의 모든 베이퍼라이져(vaporizer)에 적용이 가능하며 이를 이용한 MOCVD법으로 증착한다. 화학적 강화제를 형성한 후에 구리대신 알루미늄이나 텅스텐으로 매립을 할 수도 있다.Referring to FIG. 1E, the inside of the dual damascene pattern is embedded with copper (Cu) by organometallic chemical vapor deposition (MOCVD). In this process, since the deposition of copper (Cu) is accelerated around the concentration portion of the chemical reinforcing agent such as iodine used in the process of FIG. 1D, the inside of the dual damascene pattern is easily filled with copper (Cu). Copper buried uses direct liquid injection (DLI), Control Evaporation Mixer (CEM), It is applicable to all vaporizers of the orifice type and the spray type, and is deposited by MOCVD method using the same. After forming the chemical enhancer, it may be buried in aluminum or tungsten instead of copper.

도 1f를 참조하면, MOCVD 공정에 의해 구리매립이 완료된 후, 수소환원 열처리 공정을 실시하고, 화학적 기계적 연마(CMP) 공정을 실시하여 다마신 패턴 내부를 제외한 층간 절연막(13)의 표면에 잔류하는 구리(17) 및 확산 방지막(14)을 제거하여 구리배선(17a)을 형성한다.
Referring to FIG. 1F, after the copper filling is completed by the MOCVD process, a hydrogen reduction heat treatment process is performed, and a chemical mechanical polishing (CMP) process is performed to remain on the surface of the interlayer insulating film 13 except for the damascene pattern. The copper 17 and the diffusion barrier 14 are removed to form the copper wiring 17a.

상술한 바와 같이 본 발명은 시드층 및 화학적 강화제층을 형성하고 유기금속 화학기상증착법으로 구리를 성장시키므로써 초미세구조의 구조에서도 이중 다마신 패턴 내부로 구리를 매립을 용이하게 하므로써 신뢰성이 높은 구리배선을 형성하여 소자의 성능 및 신뢰성을 향상시킬 수 있는 효과가 있다.
As described above, the present invention forms a seed layer and a chemical reinforcing layer and grows copper by organometallic chemical vapor deposition, thereby making it easy to embed copper into a double damascene pattern even in an ultrafine structure. There is an effect that can form a wiring to improve the performance and reliability of the device.

Claims (19)

반도체 소자를 형성하기 위한 여러 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하고, 상기 층간 절연막의 소정 영역을 패터닝하여 다마신 패턴을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate having various structures for forming the semiconductor device, and patterning a predetermined region of the interlayer insulating film to form a damascene pattern; 상기 다마신 패턴을 포함한 층간 절연막 상부에 확산 방지막을 형성하는 단계;Forming a diffusion barrier over the interlayer insulating layer including the damascene pattern; 상기 확산방지막 상에 시드층을 형성한 후, 전면식각 공정을 실시하여 시드층 스페이서를 형성하는 단계;Forming a seed layer spacer by forming a seed layer on the diffusion barrier layer and then performing an entire surface etching process; 상기 시드층 스페이서 측벽에만 화학적 강화제층을 형성하는 단계;Forming a chemical enhancer layer only on the seed layer spacer sidewalls; 상기 다마신 패턴이 매립되도록 전체 구조 상부에 구리층을 형성하는 단계;Forming a copper layer on the entire structure to fill the damascene pattern; 수소환원 열처리 공정 후 화학적 기계적 연마 공정을 실시하여 구리배선을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.Forming a copper wiring by performing a chemical mechanical polishing process after the hydrogen reduction heat treatment process. 제 1 항에 있어서,The method of claim 1, 상기 다마신 패턴은 이중 다마신 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 구리배선 형성 방법.The damascene pattern is a copper wiring forming method of a semiconductor device, characterized in that formed in a double damascene method. 제 1 항에 있어서,The method of claim 1, 상기 층간 절연막은 저유전 상수값을 가지는 절연물질을 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.And the interlayer insulating layer is formed using an insulating material having a low dielectric constant value. 제 1 항에 있어서,The method of claim 1, 상기 다마신 패턴을 형성한 후 세정 공정을 실시하는 단계를 더 포함하는 것으 특징으로 하는 반도체 소자의 구리배선 형성방법.And forming a damascene pattern and then performing a cleaning process. 제 4 항에 있어서,The method of claim 4, wherein 상기 세정공정은 하부층이 W 및 Al중 어느 하나일 경우에 RF 플라즈마를 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The cleaning process is a copper wiring forming method of a semiconductor device, characterized in that performed by using an RF plasma when the lower layer is any one of W and Al. 제 4 항에 있어서,The method of claim 4, wherein 상기 세정공정은 하부층이 구리일 경우에 리액티브 세정 공정을 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.And wherein the cleaning step is performed by using a reactive cleaning step when the lower layer is copper. 제 1 항에 있어서,The method of claim 1, 상기 확산 방지막은 ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN, CVD TiAlN, CVD TiSiN, CVD TaSiN 중 적어도 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 구리배선 형성 방법.The diffusion barrier is formed of at least one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN, CVD TiAlN, CVD TiSiN, CVD TaSiN Method for forming copper wiring of device. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 시드층은 Cu, Ti 및 Al 중 어느 하나로 형성되는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The seed layer is a copper wiring forming method of a semiconductor device, characterized in that formed of any one of Cu, Ti and Al. 제 1 항에 있어서,The method of claim 1, 상기 시드층은 50 내지 500Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The seed layer is a copper wiring forming method of the semiconductor device, characterized in that formed in a thickness of 50 to 500Å. 제 1 항에 있어서,The method of claim 1, 상기 화학적 강화제층은 1 내지 600초 동안의 CECVD 공정에 의해 형성되는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The chemical reinforcing layer is a copper wiring forming method of a semiconductor device, characterized in that formed by a CECVD process for 1 to 600 seconds. 제 11 항에 있어서,The method of claim 11, 상기 CECVD 공정은 요오드 함유 액체 화합물, Hhfac1/2H2O, Hhfac 및 TMVS중 어느 하나를 촉매로 이용하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The CECVD process is a copper wiring forming method of a semiconductor device, characterized in that using any one of the iodine-containing liquid compound, Hhfac1 / 2H2O, Hhfac and TMVS as a catalyst. 제 11 항에 있어서,The method of claim 11, 상기 CECVD 공정은 pure I2, 요오드 함유 가스 및 water vapor중 어느 하나를 촉매로 이용하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The CECVD process is a copper wiring forming method of a semiconductor device, characterized in that using any one of pure I2, iodine-containing gas and water vapor as a catalyst. 제 11 항에 있어서,The method of claim 11, 상기 CECVD 공정은 액체상태의 F, Cl, Br, I, Ar, 가스상태의 F, Cl, Br, I, Ar중 어느 하나를 촉매로 이용하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The CECVD process is a copper wiring forming method of a semiconductor device, characterized in that any one of the liquid state of F, Cl, Br, I, Ar, gaseous F, Cl, Br, I, Ar as a catalyst. 제 11 항에 있어서,The method of claim 11, 상기 CECVD 공정은 액체상태인 F, Cl, Br, I, Ar와의 화합물 및 가스상태인 F, Cl, Br, I, Ar와의 화합물을 운송하는 리퀴드 딜리버리 시스템이 포함된 유기금속 화학기상증착장비에서 실시되는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The CECVD process is carried out in an organometallic chemical vapor deposition apparatus including a liquid delivery system for transporting a compound with a liquid F, Cl, Br, I, Ar and a compound with a gaseous F, Cl, Br, I, Ar. Copper wiring forming method of a semiconductor device, characterized in that. 제 11 항에 있어서,The method of claim 11, 상기 CECVD 공정은 -20 내지 300℃에서 실시되는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The CECVD process is a copper wiring forming method of a semiconductor device, characterized in that carried out at -20 to 300 ℃. 제 1 항에 있어서,The method of claim 1, 상기 구리층은 (hfac)CuVTMOS 계열, (hfac)CuDMB 계열 및 (hfac)CuTMVS 계열 중 어느 하나의 전구체를 이용한 MOCVD 방법으로 형성하는 것을 특징으로 하는 반 도체 소자의 구리배선 형성방법.The copper layer is a copper wiring forming method of a semiconductor device, characterized in that formed by the MOCVD method using any one of the precursor (hfac) CuVTMOS series, (hfac) CuDMB series and (hfac) CuTMVS series. 제 17 항에 있어서,The method of claim 17, 상기 MOCVD 공정은 다이렉트 리퀴드 인젝션(DLI), 컨트롤 에바퍼레이션 믹서(CEM), 오리피스(orifice) 방식 및 스프레이(spray) 방식중 어느 한 가지의 베이퍼라이저(vaporizer)를 갖는 구리 증착 장비에서 실시되는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The MOCVD process is performed in a copper deposition apparatus having a vaporizer of any one of a direct liquid injection (DLI), a control evolution mixer (CEM), an orifice method, and a spray method. A copper wiring forming method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 구리 대신에 알루미늄 및 텅스텐중 어느 하나를 이용하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.Copper wiring forming method of a semiconductor device, characterized in that any one of aluminum and tungsten in place of the copper.
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