KR100585227B1 - 열 방출 특성이 개선된 반도체 적층 패키지 및 이를이용한 메모리 모듈 - Google Patents
열 방출 특성이 개선된 반도체 적층 패키지 및 이를이용한 메모리 모듈 Download PDFInfo
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- KR100585227B1 KR100585227B1 KR20040016902A KR20040016902A KR100585227B1 KR 100585227 B1 KR100585227 B1 KR 100585227B1 KR 20040016902 A KR20040016902 A KR 20040016902A KR 20040016902 A KR20040016902 A KR 20040016902A KR 100585227 B1 KR100585227 B1 KR 100585227B1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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Abstract
Description
Claims (21)
- 적어도 2개의 개별 패키지들이 수직으로 적층된 반도체 적층 패키지에 있어서,상기 개별 패키지들은 각각, 하부면과 상부면을 가지는 회로기판과; 상기 회로기판의 상부면에 실장되는 집적회로 칩과; 상기 회로기판의 하부면 중앙부위에 돌출되어 형성되는 밀봉수지와; 상기 회로기판의 하부면에 형성되는 솔더 볼과; 상기 밀봉수지의 양측에 각각 위치되도록 상기 회로기판의 하부면에 부착되는 열전도층과; 상기 집적회로 칩의 상부면에 부착되는 열매개층을 포함하며,상기 개별 패키지들 중에서 상부 개별 패키지는 상기 상부 개별 패키지의 솔더 볼을 통하여 상기 하부 개별 패키지 위에 적층되고, 상기 상부 개별 패키지의 열전도층과 상기 하부 개별 패키지의 열매개층은 서로 접촉하여 열 방출 경로를 형성하는 것을 특징으로 하는 반도체 적층 패키지.
- 제1 항에 있어서,상기 개별 패키지들의 열전도층은 금속판인 것을 특징으로 하는 반도체 적층 패키지.
- 제1 항에 있어서,상기 개별 패키지들의 열매개층은 전기적으로 절연성을 가지는 것을 특징으로 하는 반도체 적층 패키지.
- 제1 항에 있어서,상기 상부 개별 패키지의 열매개층 위에 접합되는 방열판을 더 포함하는 것을 특징으로 하는 반도체 적층 패키지.
- 제1 항 또는 제4 항에 있어서,상기 하부 개별 패키지의 솔더 볼을 통하여 상기 하부 개별 패키지가 실장되는 모듈 기판을 더 포함하는 것을 특징으로 하는 반도체 적층 패키지.
- 제5 항에 있어서,상기 하부 개별 패키지의 열전도층과 상기 모듈 기판 사이에 형성되는 더미 볼을 더 포함하는 것을 특징으로 하는 반도체 적층 패키지.
- 제5 항에 있어서,상기 하부 개별 패키지의 회로기판과 상기 모듈 기판 사이에 채워지는 언더필 물질을 더 포함하는 것을 특징으로 하는 반도체 적층 패키지.
- 제1 항에 있어서,상기 하부 개별 패키지의 회로기판과 상기 상부 개별 패키지의 회로기판 사이에 채워지는 언더필 물질을 더 포함하는 것을 특징으로 하는 반도체 적층 패키 지.
- 적어도 2개의 개별 패키지들이 수직으로 적층된 반도체 적층 패키지에 있어서,상기 개별 패키지들 중에서 제1 개별 패키지는, 하부면과 상부면을 가지는 회로기판과; 상기 회로기판의 하부면에 실장되는 집적회로 칩과; 상기 회로기판의 상부면 중앙부위에 돌출되어 형성되는 밀봉수지와; 상기 회로기판의 하부면에 형성되는 솔더 볼을 포함하며,상기 개별 패키지들 중에서 제2 개별 패키지는, 하부면과 상부면을 가지는 회로기판과; 상기 회로기판의 상부면에 실장되는 집적회로 칩과; 상기 회로기판의 하부면의 중앙부위에 돌출되어 형성되는 밀봉수지와; ㅂ상기 회로기판의 하부면에 형성되는 솔더 볼을 포함하며,상기 제2 개별 패키지는 상기 제2 개별 패키지의 솔더 볼을 통하여 상기 제1 개별 패키지 위에 적층되어, 상기 제1 개별 패키지는 아래쪽으로 열 방출 경로가 형성되고 상기 제2 개별 패키지는 위쪽으로 열 방출 경로가 형성되는 것을 특징으로 하는 반도체 적층 패키지.
- 제9 항에 있어서,상기 제1 개별 패키지는 상부 개별 패키지와 하부 개별 패키지를 포함하고, 상기 상부 개별 패키지와 하부 개별 패키지는 각각, 상기 회로기판의 상부면에 부착되는 열전도층과; 상기 집적회로 칩의 하부면에 부착되는 열매개층을 포함하며,상기 상부 개별 패키지는 상기 상부 개별 패키지의 솔더 볼을 통하여 상기 하부 개별 패키지 위에 적층되고, 상기 상부 개별 패키지의 열매개층과 상기 하부 개별 패키지의 열전도층은 서로 접촉하여 열 방출 경로를 형성하는 것을 특징으로 하는 반도체 적층 패키지.
- 제9 항에 있어서,상기 제2 개별 패키지는 상부 개별 패키지와 하부 개별 패키지를 포함하고, 상기 상부 개별 패키지와 하부 개별 패키지는 각각, 상기 회로기판의 하부면에 부착되는 열전도층과; 상기 집적회로 칩의 상부면에 부착되는 열매개층을 포함하며,상기 상부 개별 패키지는 상기 상부 개별 패키지의 솔더 볼을 통하여 상기 하부 개별 패키지 위에 적층되고, 상기 상부 개별 패키지의 열전도층과 상기 하부 개별 패키지의 열매개층은 서로 접촉하여 열 방출 경로를 형성하는 것을 특징으로 하는 반도체 적층 패키지.
- 제10 항 또는 제11 항에 있어서,상기 개별 패키지들의 열전도층은 금속판인 것을 특징으로 하는 반도체 적층 패키지.
- 제10 항 또는 제11 항에 있어서,상기 개별 패키지들의 열매개층은 전기적으로 절연성을 가지는 것을 특징으로 하는 반도체 적층 패키지.
- 제9 항에 있어서,상기 제2 개별 패키지의 집적회로 칩 위에 접합되는 방열판을 더 포함하는 것을 특징으로 하는 반도체 적층 패키지.
- 제9 항 또는 제14 항에 있어서,상기 제1 개별 패키지의 솔더 볼을 통하여 상기 제1 개별 패키지가 실장되는 모듈 기판을 더 포함하는 것을 특징으로 하는 반도체 적층 패키지.
- 제15 항에 있어서,상기 제1 개별 패키지의 회로기판과 상기 모듈 기판 사이에 형성되는 더미 볼을 더 포함하는 것을 특징으로 하는 반도체 적층 패키지.
- 제15 항에 있어서,상기 제1 개별 패키지의 회로기판과 상기 모듈 기판 사이에 채워지는 언더필 물질을 더 포함하는 것을 특징으로 하는 반도체 적층 패키지.
- 제9 항에 있어서,상기 제1 개별 패키지의 회로기판과 상기 제2 개별 패키지의 회로기판 사이에 채워지는 언더필 물질을 더 포함하는 것을 특징으로 하는 반도체 적층 패키지.
- 상부면과 하부면을 가지는 모듈 기판을 포함하며,제1 항 또는 제9 항에 기재된 반도체 적층 패키지가 적어도 2개 이상 상기 모듈 기판의 상부면과 하부면의 적어도 한 면에 실장되는 메모리 모듈.
- 제19 항에 있어서,상기 반도체 적층 패키지의 최상부에 각각 접합되는 방열판을 더 포함하는 것을 특징으로 하는 메모리 모듈.
- 제19 항에 있어서,상기 반도체 적층 패키지의 최상부에 전체적으로 접합되는 방열판을 더 포함하는 것을 특징으로 하는 메모리 모듈.
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