KR100557978B1 - Fabricating method of semiconductor device - Google Patents

Fabricating method of semiconductor device Download PDF

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KR100557978B1
KR100557978B1 KR1019990035625A KR19990035625A KR100557978B1 KR 100557978 B1 KR100557978 B1 KR 100557978B1 KR 1019990035625 A KR1019990035625 A KR 1019990035625A KR 19990035625 A KR19990035625 A KR 19990035625A KR 100557978 B1 KR100557978 B1 KR 100557978B1
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forming
gate electrode
silicide layer
semiconductor device
gate
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KR1019990035625A
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Korean (ko)
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KR20010019291A (en
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남상혁
김홍선
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 종래에는 소자간 격리영역을 형성하는 공정과 게이트를 형성하는 공정이 개별적으로 진행되어 공정이 복잡하고, 액티브영역의 가장자리가 평탄하게 처리되지 않아 전계 집중으로 인한 트랜지스터의 오동작을 유발하는 문제점이 있었다. 따라서, 본 발명은 반도체기판의 상부에 게이트산화막과 게이트전극을 순차적으로 형성한 다음 사진식각공정을 통해 게이트전극과 게이트산화막을 식각하고, 계속해서 반도체기판을 정해진 깊이로 식각하는 공정과; 상기 결과물의 상부에 제1절연막을 형성한 다음 게이트전극이 일정한 두께로 식각될 때까지 평탄화하는 공정과; 상기 결과물의 상부에 실리사이드층을 형성한 다음 패터닝하는 공정과; 상기 결과물의 상부에 층간절연막을 통해 실리사이드층과 선택적으로 접속되는 배선을 형성하는 공정으로 이루어지는 반도체소자의 제조방법을 통해 소자간 격리영역과 게이트의 형성을 동시에 진행하여 공정을 단순화함과 아울러 액티브영역의 가장자리를 평탄하게 처리하여 트랜지스터의 오동작을 억제할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In the related art, a process of forming an isolation region between devices and a process of forming a gate are performed separately, and the process is complicated. There was a problem of causing a malfunction of the transistor. Accordingly, the present invention comprises the steps of sequentially forming a gate oxide film and a gate electrode on the semiconductor substrate, and then etching the gate electrode and the gate oxide film through a photolithography process, and subsequently etching the semiconductor substrate to a predetermined depth; Forming a first insulating layer on the resultant and then planarizing the gate electrode until the gate electrode is etched to a predetermined thickness; Forming a silicide layer on the resultant and then patterning the silicide layer; Through the method of manufacturing a semiconductor device comprising a step of forming a wiring that is selectively connected to the silicide layer through the interlayer insulating film on the upper part of the resultant, the formation of the isolation region and the gate between the devices at the same time to simplify the process and the active region By treating the edges of the transistors evenly, it is possible to suppress malfunction of the transistors.

Description

반도체소자의 제조방법{FABRICATING METHOD OF SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {FABRICATING METHOD OF SEMICONDUCTOR DEVICE}

도1a 내지 도1f는 종래 반도체소자의 제조방법을 보인 수순단면도.1A to 1F are cross-sectional views showing a conventional method for manufacturing a semiconductor device.

도2a 내지 도2g는 본 발명의 일 실시예를 보인 수순단면도.Figures 2a to 2g is a cross-sectional view showing an embodiment of the present invention.

***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***

11:반도체기판 12:게이트산화막11: semiconductor substrate 12: gate oxide film

13:게이트전극 14:제1절연막13: gate electrode 14: first insulating film

15:실리사이드층 16:층간절연막15: silicide layer 16: interlayer insulating film

17:배선17: Wiring

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 소자간 격리영역과 게이트의 형성을 동시에 진행하여 공정을 단순함과 아울러 특성을 향상시키기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which the formation of isolation regions and gates between devices is performed simultaneously to simplify the process and to improve characteristics.

종래 반도체소자의 제조방법을 도1a 내지 도1f의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will be described in detail with reference to the procedure cross-sectional view of FIGS. 1A to 1F.

먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 제1절연막(2)을 형성한 다음 사진식각공정을 적용하여 제1절연막(2)의 일부를 식각함으로써, 반도체소자의 액티브영역을 정의한다.First, as shown in FIG. 1A, the first insulating film 2 is formed on the semiconductor substrate 1, and then a portion of the first insulating film 2 is etched by applying a photolithography process to thereby form an active region of the semiconductor device. Define.

그리고, 도1b에 도시한 바와같이 상기 식각된 제1절연막(2)을 마스크로 이용하여 반도체기판(1)을 식각한다.1B, the semiconductor substrate 1 is etched using the etched first insulating layer 2 as a mask.

그리고, 도1c에 도시한 바와같이 상기 반도체기판(1)이 식각된 결과물의 상부전면에 제2절연막(3)을 형성한다.As shown in FIG. 1C, the second insulating layer 3 is formed on the upper surface of the resultant of the semiconductor substrate 1 being etched.

그리고, 도1d에 도시한 바와같이 상기 제1절연막(2)이 어느정도 식각될 때까지 제2절연막(3)을 화학기계적 연마하여 평탄화한다.As shown in FIG. 1D, the second insulating film 3 is chemically polished and planarized until the first insulating film 2 is etched to some extent.

그리고, 도1e에 도시한 바와같이 상기 제1절연막(2)을 제거한 다음 상부전면에 게이트산화막(4)과 게이트전극(5)을 순차적으로 형성한다.As shown in FIG. 1E, the first insulating film 2 is removed, and then the gate oxide film 4 and the gate electrode 5 are sequentially formed on the upper surface.

그리고, 도1f에 도시한 바와같이 상기 게이트전극(5)을 패터닝한 다음 상부 전면에 제3절연막(6)을 형성하고, 일부를 식각하여 게이트전극(5)이 노출되는 콘택홀을 형성한 다음 상부전면에 콘택홀이 채워지도록 배선(7)을 형성한다.As shown in FIG. 1F, after the gate electrode 5 is patterned, a third insulating layer 6 is formed on the entire upper surface, and a portion of the gate electrode 5 is etched to form a contact hole through which the gate electrode 5 is exposed. The wiring 7 is formed to fill the contact hole in the upper front surface.

그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 소자간 격리영역을 형성하는 공정과 게이트를 형성하는 공정이 개별적으로 진행되어 공정이 복잡하고, 액티브영역의 가장자리가 평탄하게 처리되지 않아 전계 집중으로 인한 트랜지스터의 오동작을 유발하는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above, the process of forming the isolation region between the elements and the process of forming the gate are performed separately, and the process is complicated. There was a problem causing malfunction of the transistor.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 소자간 격리영역과 게이트의 형성을 동시에 진행하여 공정을 단순화함과 아울러 액티브영역의 가장자리를 평탄하게 처리하여 트랜지스터의 오동작을 억제할 수 있는 반도체소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to simplify the process by simultaneously forming the isolation region and the gate between the elements and to smoothly process the edges of the active region. The present invention provides a method for manufacturing a semiconductor device that can suppress a malfunction of a transistor.

상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판의 상부에 게이트산화막과 게이트전극을 순차적으로 형성한 다음 사진식각공정을 통해 게이트전극과 게이트산화막을 식각하고, 계속해서 반도체기판을 정해진 깊이로 식각하는 공정과; 상기 결과물의 상부에 제1절연막을 형성한 다음 게이트전극이 일정한 두께로 식각될 때까지 평탄화하는 공정과; 상기 결과물의 상부에 실리사이드층을 형성한 후 상기 실리사이드층을 상기 게이트전극의 상부 뿐만 아니라 그 양측 제1절연막의 상부에도 일부가 형성되도록 패터닝하는 공정과; 상기 결과물의 상부에 층간절연막을 통해 실리사이드층과 선택적으로 접속되는 배선을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.In order to achieve the object of the present invention as described above, a method of manufacturing a semiconductor device includes sequentially forming a gate oxide film and a gate electrode on an upper surface of a semiconductor substrate, and then etching the gate electrode and the gate oxide film through a photolithography process. Etching the semiconductor substrate to a predetermined depth; Forming a first insulating layer on the resultant and then planarizing the gate electrode until the gate electrode is etched to a predetermined thickness; Forming a silicide layer on top of the resultant, and then patterning the silicide layer so that a part of the silicide layer is formed not only on the gate electrode but also on both sides of the first insulating layer; And forming a wiring selectively connected to the silicide layer through the interlayer insulating film on the resultant.

상기한 바와같은 본 발명에 의한 반도체소자의 제조방법을 도2a 내지 도2g의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.The method for manufacturing a semiconductor device according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 2A to 2G as an embodiment.

먼저, 도2a에 도시한 바와같이 반도체기판(11)의 상부에 순차적으로 게이트산화막(12)과 게이트전극(13)을 형성한다. 이때, 게이트전극(13) 물질로는 폴리실리콘을 적용하는 것이 바람직하다.First, as shown in FIG. 2A, the gate oxide film 12 and the gate electrode 13 are sequentially formed on the semiconductor substrate 11. In this case, it is preferable to apply polysilicon as the gate electrode 13 material.

그리고, 도2b에 도시한 바와같이 상기 게이트전극(13)과 게이트산화막(12)이 형성된 구조물 상에 사진식각공정을 적용하여 게이트전극(13)과 게이트산화막(12)을 식각하고, 계속해서 반도체기판(11)을 정해진 깊이로 식각하여 반도체소자의 액티브영역을 정의한다.As shown in FIG. 2B, the gate electrode 13 and the gate oxide layer 12 are etched by applying a photolithography process to the structure on which the gate electrode 13 and the gate oxide layer 12 are formed. The substrate 11 is etched to a predetermined depth to define an active region of the semiconductor device.

그리고, 도2c에 도시한 바와같이 상기 액티브영역이 정의된 반도체기판(11)의 상부에 제1절연막(14)을 형성한다.As shown in FIG. 2C, the first insulating layer 14 is formed on the semiconductor substrate 11 in which the active region is defined.

그리고, 도2d에 도시한 바와같이 상기 제1절연막(14)이 형성된 구조물 상에 화학기계적 연마를 적용하여 상기 게이트전극(13)이 일정한 두께로 식각될 때까지 평탄화한다.As shown in FIG. 2D, chemical mechanical polishing is applied to the structure on which the first insulating layer 14 is formed to be flattened until the gate electrode 13 is etched to a predetermined thickness.

그리고, 도2e에 도시한 바와같이 상기 평탄화된 구조물의 상부에 실리사이드층(15)을 형성한다.As illustrated in FIG. 2E, the silicide layer 15 is formed on the planarized structure.

그리고, 도2f에 도시한 바와같이 상기 실리사이드층(15)을 패터닝한다. 이때, 실리사이드층(15)은 게이트전극(13)의 상부 뿐만 아니라 양측 제1절연막(14)의 상부에도 일부가 형성되도록 패터닝한다.Then, the silicide layer 15 is patterned as shown in FIG. 2F. In this case, the silicide layer 15 is patterned so that a portion is formed not only on the gate electrode 13 but also on both sides of the first insulating layer 14.

그리고, 도2g에 도시한 바와같이 상기 실리사이드층(15)이 패터닝된 구조물 의 상부에 층간절연막(16)을 형성하고, 일부를 식각하여 실리사이드층(15)이 노출되는 콘택홀을 형성한 다음 콘택홀이 채워지도록 배선(17)을 형성한다.As shown in FIG. 2G, an interlayer insulating layer 16 is formed on the structure on which the silicide layer 15 is patterned, and a portion thereof is etched to form a contact hole through which the silicide layer 15 is exposed. The wiring 17 is formed to fill the hole.

한편, 트랜지스터의 문턱전압(Vt) 조절용 불순물 이온주입은 상기 게이트산화막을 형성하기 전에 실시하거나, 상기 제1절연막(14)을 평탄화한 다음에 실시하거나 또는 상기 실리사이드층(15)을 형성한 다음에 선택적으로 실시할 수 있다.Impurity ion implantation for adjusting the threshold voltage Vt of the transistor may be performed before the gate oxide film is formed, or after the first insulating film 14 is planarized, or after the silicide layer 15 is formed. It can be carried out selectively.

상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 소자간 격리영역과 게이트의 형성을 동시에 진행하여 공정을 단순화함과 아울러 액티브영역의 가장자리를 평탄하게 처리하여 트랜지스터의 오동작을 억제할 수 있는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above simplifies the process by simultaneously forming the isolation region and the gate between the elements and the effect of suppressing the malfunction of the transistor by smoothing the edge of the active region. There is.

Claims (6)

반도체기판의 상부에 게이트산화막과 게이트전극을 순차적으로 형성한 다음 사진식각공정을 통해 게이트전극과 게이트산화막을 식각하고, 계속해서 반도체기판을 정해진 깊이로 식각하는 공정과; Sequentially forming a gate oxide film and a gate electrode on the semiconductor substrate, followed by etching the gate electrode and the gate oxide film through a photolithography process, and subsequently etching the semiconductor substrate to a predetermined depth; 상기 결과물의 상부에 제1절연막을 형성한 다음 게이트전극이 일정한 두께로 식각될 때까지 평탄화하는 공정과; Forming a first insulating layer on the resultant and then planarizing the gate electrode until the gate electrode is etched to a predetermined thickness; 상기 결과물의 상부에 실리사이드층을 형성한 후 상기 실리사이드층을 상기 게이트전극의 상부 뿐만 아니라 그 양측 제1절연막의 상부에도 일부가 형성되도록 패터닝하는 공정과;Forming a silicide layer on top of the resultant, and then patterning the silicide layer so that a part of the silicide layer is formed not only on the gate electrode but also on both sides of the first insulating layer; 상기 결과물의 상부에 층간절연막을 통해 실리사이드층과 선택적으로 접속되는 배선을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.And forming a wiring selectively connected to the silicide layer through the interlayer insulating film on the resultant. 제 1 항에 있어서, 상기 게이트전극은 폴리실리콘을 증착하여 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the gate electrode is formed by depositing polysilicon. 삭제delete 제 1 항에 있어서, 상기 게이트산화막을 형성하기 전에 문턱전압 조절용 불순물 이온주입 공정을 더 포함하여 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, further comprising a step of implanting impurity ions for adjusting a threshold voltage before forming said gate oxide film. 제 1 항에 있어서, 상기 제1절연막을 평탄화한 다음에 문턱전압 조절용 불순물 이온주입 공정을 더 포함하여 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, further comprising a step of implanting impurity ions for adjusting a threshold voltage after planarizing the first insulating film. 제 1 항에 있어서, 상기 실리사이드층을 형성한 다음에 문턱전압 조절용 불순물 이온주입 공정을 더 포함하여 이루어지는 것을 특징으로 하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, further comprising a step of implanting impurity ions for adjusting the threshold voltage after forming the silicide layer.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177239A (en) * 1992-07-30 1994-06-24 Nec Corp Manufacture of trench element isolation structure
JPH11186379A (en) * 1997-12-19 1999-07-09 Sony Corp Manufacture of semiconductor device
KR20000024914A (en) * 1998-10-02 2000-05-06 김영환 Method for forming isolating layer of semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177239A (en) * 1992-07-30 1994-06-24 Nec Corp Manufacture of trench element isolation structure
JPH11186379A (en) * 1997-12-19 1999-07-09 Sony Corp Manufacture of semiconductor device
KR20000024914A (en) * 1998-10-02 2000-05-06 김영환 Method for forming isolating layer of semiconductor devices

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