KR100480236B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100480236B1 KR100480236B1 KR10-2003-0044010A KR20030044010A KR100480236B1 KR 100480236 B1 KR100480236 B1 KR 100480236B1 KR 20030044010 A KR20030044010 A KR 20030044010A KR 100480236 B1 KR100480236 B1 KR 100480236B1
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- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 239000007943 implant Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 239000007772 electrode material Substances 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000010405 reoxidation reaction Methods 0.000 claims description 3
- 230000035876 healing Effects 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 8
- 238000003860 storage Methods 0.000 abstract description 8
- 230000014759 maintenance of location Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000000463 material Substances 0.000 description 15
- 238000000151 deposition Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Manufacturing & Machinery (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 채널 임플란트 공정시 스토리지 노드에 이온이 도핑되는 것을 방지하여 전계 증가에 의한 데이터 보유 시간 감소를 방지하기 위한 반도체 소자의 제조 방법에 관한 것으로, 소정의 하부 구조가 형성된 반도체 기판 상에 게이트 산화막과 게이트 전극 물질 및 층간 절연막을 순차로 형성하는 단계와, 상기 층간 절연막을 식각하여 채널이 형성될 부분을 오픈하는 단계와, 상기 채널이 형성될 영역이 오픈된 결과물에 임플란트 공정을 진행하여 실리콘 기판에 채널 영역을 형성하는 단계와, 상기 층간 절연막이 식각된 부분에 질화막을 매립한 후 평탄화하는 단계와, 상기 층간 절연막을 습식 식각 공정으로 제거하는 단계와, 상기 질화막을 마스크로 이용한 식각 공정을 진행하여 게이트를 패터닝하는 단계를 포함하여 구성된다.The present invention relates to a method of fabricating a semiconductor device for preventing a doping of ions in a storage node during a channel implant process, thereby reducing data retention time due to an increase in electric field. And sequentially forming a gate electrode material and an interlayer insulating film, etching the interlayer insulating film to open a portion where a channel is to be formed, and performing an implant process on a result of opening the region where the channel is to be formed. Forming a channel region in the trench, embedding a nitride film in a portion where the interlayer insulating film is etched, and then planarizing, removing the interlayer insulating film by a wet etching process, and etching using the nitride film as a mask. Patterning the gates.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 채널 이온 주입을 실시함에 있어서, 층간 절연막을 게이트 상부에 형성한 후 채널 영역만 오픈시켜 임플란트 공정을 진행함으로써, 스토리지 노드 정션부까지 이온이 도핑되는 것을 방지하여 전계의 증가를 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in performing channel ion implantation, by forming an interlayer insulating film on the gate and then opening only the channel region to proceed with an implant process, the ion to the storage node junction portion. The present invention relates to a method for manufacturing a semiconductor device capable of preventing the doping and preventing an increase in the electric field.
종래의 모스 트랜지스터는, 반도체 소자들이 고집적화되어 감에 따라, 게이트 전극의 폭도 0.1㎛ 급으로 줄어들게 되고, 이에 따라 모스 트랜지스터의 채널의 길이 또한 현저하게 감소되었다. 이로 인하여, 모스 트랜지스터의 소오스와 드레인 사이에는 채널에 강한 수평 전계가 걸리게 됨으로써, Electricfield = Voltage / Length의 식에 의해 강한 전계 내의 전자들은 높은 에너지를 갖게 된다. In the conventional MOS transistor, as the semiconductor devices are highly integrated, the width of the gate electrode is reduced to 0.1 占 퐉, and thus the channel length of the MOS transistor is also significantly reduced. As a result, a strong horizontal electric field is applied to the channel between the source and the drain of the MOS transistor, so that the electrons in the strong electric field have high energy by the expression of Electricfield = Voltage / Length.
이렇게 높은 에너지를 갖는 전자(이하, 핫 캐리어)들은 모스 트랜지스터의 동작시, 게이트 절연막을 관통하게 되고, 채널 거리가 짧아짐에 따라 드레인에서의 공핍 영역이 소오스 영역을 관통하게 되는 펀치 스루(punch through)현상까지 발생시킨다. These high energy electrons (hereinafter, hot carriers) penetrate through the gate insulating layer during operation of the MOS transistor, and punch through through which the depletion region in the drain penetrates the source region as the channel distance becomes shorter. The phenomenon occurs.
이러한 종래 기술에 의한 모스 트랜지스터의 문제점을 하기 도면을 참조하여 상세히 설명한다.The problem of the MOS transistor according to the prior art will be described in detail with reference to the following drawings.
도1은 종래 기술에 의한 반도체 소자의 제조 방법의 일례를 나타낸 도면이다.1 is a view showing an example of a method for manufacturing a semiconductor device according to the prior art.
우선, 도1에 도시된 바와 같이 실리콘 기판(100) 상에 소자 분리막(110)을 형성하여 액티브 영역과 필드 영역을 구분한다. 그런 다음, 소정의 열공정을 진행하여 게이트 산화막(120)을 형성한 후 임플란트 공정을 진행하여 액티브 영역에 채널 영역(130)을 형성한다. First, as shown in FIG. 1, an isolation layer 110 is formed on a silicon substrate 100 to distinguish an active region from a field region. Thereafter, a predetermined thermal process is performed to form the gate oxide film 120, and then an implant process is performed to form the channel region 130 in the active region.
그 후, 그 상부에 제 1 게이트 물질(140)로 폴리 실리콘막을, 제 1 게이트 물질 상부에 제 2 게이트 물질(150)로 텅스텐 실리사이드를 차례로 증착한다. 그리고, 상기 제 2 게이트 물질(160) 상부에 하드 마스크로 이용할 질화막(160)을 증착하고 소정의 사진 및 식각 공정을 진행하여 상기 질화막을 패터닝한다.A polysilicon film is then deposited on top of the first gate material 140 and tungsten silicide on top of the first gate material with a second gate material 150. The nitride layer 160 to be used as a hard mask is deposited on the second gate material 160, and the nitride layer is patterned by performing a predetermined photo and etching process.
상기 패터닝된 질화막(160)을 이용하여 상기 제 2 게이트 물질 및 제 1 게이트 물질을 식각해서 게이트 전극을 형성한다. The second gate material and the first gate material are etched using the patterned nitride film 160 to form a gate electrode.
이러한 종래 기술에 따른 채널 형성 방법에 의하면, 셀 트랜지스터의 채널 영역 이외의 스토리지 노드 정션쪽으로도 도핑되어, 소오스/드레인 형성후에 스토리지 노드 정션 쪽에 고 전계 영역이 생기게 되어, 결국 필드의 접합 누설이 증가하게 되어 데이터의 보유 시간이 짧아지게 되는 문제점이 발생한다.According to the channel forming method according to the related art, a high electric field region is formed on the storage node junction side after the source / drain formation, which is doped to the storage node junction other than the channel region of the cell transistor, thereby increasing the junction leakage of the field. This results in a problem that the retention time of data is shortened.
도2는 종래 기술에 의한 반도체 소자의 제조 방법의 다른 예를 나타낸 도면이다. 2 is a view showing another example of a method of manufacturing a semiconductor device according to the prior art.
우선, 도2에 도시된 바와 같이 실리콘 기판(100) 상에 소자 분리막(110)을 형성하여 액티브 영역과 필드 영역을 구분한다. 그런 다음, 소정의 열공정을 진행하여 게이트 산화막(120)을 형성한다. First, as shown in FIG. 2, the device isolation layer 110 is formed on the silicon substrate 100 to distinguish the active region from the field region. Thereafter, a predetermined thermal process is performed to form the gate oxide film 120.
이어서, 상기 게이트 산화막(120) 상부에 층간 절연막(170)을 증착한 다음 게이트가 형성될 영역이 오픈되도록 상기 층간 절연막(170)을 식각하여 홀(180)을 형성한다. 그리고, 상기 결과물에 채널 임플란트 공정을 진행하여 액티브 영역에 채널 영역(190)을 형성한다. Subsequently, the interlayer insulating layer 170 is deposited on the gate oxide layer 120, and the hole 180 is formed by etching the interlayer insulating layer 170 to open the region where the gate is to be formed. The channel implant process is performed on the resultant to form the channel region 190 in the active region.
그리고 나서, 후속 공정으로 상기 홀(180)에 게이트 물질인 폴리실리콘(미도시함)과 텅스텐 실리사이드(미도시함)을 이용한 갭필 공정을 차례로 실시하여 게이트 전극(미도시함)을 형성한다.Thereafter, a gap fill process using polysilicon (not shown) and tungsten silicide (not shown), which are gate materials, is sequentially performed in the hole 180 to form a gate electrode (not shown).
그런데, 이러한 리버스(Reverse) 게이트 형성에 의한 채널 형성 방법에 의하면, 층간 절연막에 홀을 형성한 후 게이트 물질을 채워가기 때문에 각 층마다 증착후에 에치백 공정을 계속 진행해하므로 공정 단계가 증가할 뿐만 아니라, 에스펙트비(Aspect ratio)가 큰 경우에 갭필 과정에서 보이드가 발생하는 문제점이 있었다.However, according to such a channel forming method by forming a reverse gate, since the gate material is filled after forming a hole in the interlayer insulating film, the etch back process is continued after deposition for each layer. There is a problem that voids occur in the gapfill process when the aspect ratio is large.
상기와 같은 문제점을 해결하기 위한 본 발명은 게이트 물질 상부에 하드 마스크 대신 층간 절연막을 형성하고 채널 형성 부위의 층간 절연막을 제거한 다음 임플란트 공정을 진행한 후에, 상기 층간 절연막이 식각된 부분에 하드마스크용 질화막을 증착해서 이를 이용한 식각 공정으로 게이트 패턴을 형성하여 스토리지 노드 정션에 불필요하게 이온 도핑이 되는 것을 방지할 수 있도록 하는 채널 형성 방법을 제공하기 위한 것이다. In order to solve the above problems, the present invention forms an interlayer insulating film instead of a hard mask on the gate material, removes the interlayer insulating film at the channel forming region, and then performs an implant process, whereby the interlayer insulating film is etched. The present invention provides a channel forming method for forming a gate pattern by depositing a nitride film and forming an gate pattern to prevent unnecessary ion doping at a storage node junction.
상기와 같은 목적을 실현하기 위한 본 발명은 소정의 하부 구조가 형성된 반도체 기판 상에 게이트 산화막과 게이트 전극 물질 및 층간 절연막을 순차로 형성하는 단계와, 상기 층간 절연막을 식각하여 채널이 형성될 부분을 오픈하는 단계와, 상기 채널이 형성될 영역이 오픈된 결과물에 임플란트 공정을 진행하여 실리콘 기판에 채널 영역을 형성하는 단계와, 상기 층간 절연막이 식각된 부분에 질화막을 매립한 후 평탄화하는 단계와, 상기 층간 절연막을 습식 식각 공정으로 제거하는 단계와, 상기 질화막을 마스크로 이용한 식각 공정을 진행하여 게이트를 패터닝하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법에 관한 것이다.According to an aspect of the present invention, a gate oxide film, a gate electrode material, and an interlayer insulating film are sequentially formed on a semiconductor substrate on which a predetermined substructure is formed, and a portion where a channel is to be formed by etching the interlayer insulating film. Opening a channel, forming a channel region on a silicon substrate by performing an implant process on a result of the opening of the region where the channel is to be formed, filling a nitride film in a portion where the interlayer insulating layer is etched, and then planarizing it; And removing the interlayer insulating layer by a wet etching process and performing an etching process using the nitride layer as a mask to pattern the gate.
상기 본 발명에 의한 반도체 소자의 제조 방법에서는, 게이트 패터닝 공정후 재산화 공정을 더 진행함으로써 임플란트 공정과 게이트 식각 공정에 의한 데미지를 치유할 수 있다.In the method for manufacturing a semiconductor device according to the present invention, the damage caused by the implant process and the gate etching process can be cured by further performing the reoxidation process after the gate patterning process.
이와 같은 본 발명에 의한 반도체 소자의 제조 방법에 있어서는 채널 영역만을 오픈 되도록 한 후 임플란트 공정을 진행함으로써, 스토리지 노드 정션부까지 불필요한 이온 도핑이 이루어지지 않도록 함으로써 전계를 감소시켜 데이터 보유 시간을 증가시킬 수 있다.In the method of manufacturing a semiconductor device according to the present invention, by opening only the channel region and then performing an implant process, an unnecessary ion doping is not performed to the storage node junction, thereby reducing the electric field and increasing data retention time. have.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도3a 내지 도3f는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 공정 단면도들이다.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
우선, 도3a에 도시된 바와 같이 실리콘 기판(200)에 소정의 소자 분리 공정으로 필드 산화막(210)을 형성하여 액티브 영역과 필드 영역을 구분한 후 게이트 산화막(220)을 형성한다. 상기 게이트 산화막(220) 상부에 게이트 폴리실리콘(230)과 게이트 텅스텐 실리사이드(240)를 증착한 후 층간 절연막(250)을 순차로 증착한다.First, as shown in FIG. 3A, the field oxide layer 210 is formed on the silicon substrate 200 by a predetermined device isolation process to separate the active region from the field region, and then the gate oxide layer 220 is formed. After the gate polysilicon 230 and the gate tungsten silicide 240 are deposited on the gate oxide layer 220, the interlayer insulating layer 250 is sequentially deposited.
이어서, 채널이 형성될 영역이 오픈 되도록 포토레지스트 패턴(PR)을 형성한다.Subsequently, the photoresist pattern PR is formed to open the region where the channel is to be formed.
그런 다음, 도3b에 도시된 바와 같이 상기 포토레지스트 패턴(PR)을 이용하여 층간 절연막(250)을 식각한 후 도3c에 도시된 바와 같이 임플란트 공정을 진행하여 실리콘 기판의 액티브 영역에 채널 영역(260)을 형성한다. 이때, 상기 층간 절연막이 식각된 부분만 채널 도핑이 이루어지게 된다.Next, as shown in FIG. 3B, the interlayer insulating layer 250 is etched using the photoresist pattern PR, and then an implant process is performed as shown in FIG. 3C, and the channel region ( 260 is formed. In this case, channel doping is performed only in the portion where the interlayer insulating layer is etched.
그리고 나서, 도3d에 도시된 바와 같이 상기 층간 절연막(250)이 식각된 부분을 하드 마스크용 질화막(270)을 증착하여 매립한 후 CMP 공정을 진행하여 평탄화한다. Next, as shown in FIG. 3D, the portion where the interlayer insulating layer 250 is etched is deposited by filling the nitride film 270 for hard mask, and then planarized by performing a CMP process.
이어, 도3e에 도시된 바와 같이 층간 절연막(250)을 습식 식각 공정을 진행하여 제거한 후 도3f에 도시된 바와 같이 질화막(270)을 마스크로 이용한 식각 공정을 진행하여 일반적인 게이트를 형성하고, 임플란트 공정 및 게이트 식각 공정에 의한 데미지를 치유하기 위한 재산화 공정을 진행한다.Subsequently, as shown in FIG. 3E, the interlayer insulating layer 250 is removed by performing a wet etching process, and as shown in FIG. 3F, an etching process using the nitride layer 270 as a mask is performed to form a general gate and an implant. A reoxidation process is performed to heal damage caused by the process and the gate etching process.
이와 같이 본 발명은 리버스(Reverse) 게이트를 형성함에 있어서, 하드 마스크를 증착하는 대신 층간 절연막을 증착해서 하부의 채널 영역만 오픈되도록 층간 절연막을 식각한 후에 채널 임플란트 공정을 진행함으로써, 스토리지 노드 정션부까지 불필요한 이온 도핑이 이루어지지 않도록 할 뿐만 아니라, 식각된 층간 절연막에 하드마스크 물질을 증착한 후 이를 이용하여 게이트를 패터닝함으로써, 리버스 게이트의 게이트 물질 갭필 공정시의 보이드 발생을 방지할 수 있고 게이트 물질 증착시 마다 실시하는 에치백 공정시 생략되므로 공정 단계를 감소시킬 수 있다.As described above, in forming the reverse gate, the storage node junction portion is formed by etching the interlayer insulating layer so that only the lower channel region is opened by depositing the interlayer insulating layer instead of depositing a hard mask. In addition to preventing unnecessary ion doping, the gate is patterned using the hard mask material deposited on the etched interlayer insulating film, thereby preventing voids in the gate material gapfill process of the reverse gate and Since it is omitted during the etchback process performed at every deposition, process steps can be reduced.
상기한 바와 같이 본 발명은 이와 같이 본 발명은 채널 영역에만 임플란트 공정을 진행하여 스토리지 노드 정션부까지 불필요한 이온 도핑이 이루어지지 않도록 함으로써 전계를 감소시켜 데이터 보유 시간을 증가시킬 수 이점이 있다.As described above, the present invention has the advantage that the present invention can increase the data retention time by reducing the electric field by performing an implant process only in the channel region so that unnecessary ion doping is not performed to the storage node junction.
또한, 식각된 층간 절연막에 하드마스크 물질을 증착한 후 이를 이용하여 게이트를 패터닝함으로써, 리버스 게이트의 게이트 물질 갭필 공정시의 보이드 발생을 방지할 수 있고 게이트 물질 증착시 마다 실시하는 에치백 공정시 생략되므로 공정 단계를 감소시킬 수 있는 이점이 있다.In addition, by depositing a hard mask material on the etched interlayer insulating film and patterning the gate using the hard mask material, void generation during the gate material gap fill process of the reverse gate can be prevented and omitted during the etch back process performed during the gate material deposition. Therefore, there is an advantage that can reduce the process step.
도1은 종래 기술에 의한 반도체 소자의 제조 방법의 제 1 실시예를 나타낸 도면이다.1 is a view showing a first embodiment of a method for manufacturing a semiconductor device according to the prior art.
도2는 종래 기술에 의한 반도체 소자의 제조 방법의 제 2 실시예를 나타낸 도면이다.2 is a view showing a second embodiment of the method for manufacturing a semiconductor device according to the prior art.
도3a 내지 도3f는 본 발명에 의한 반도체 소자의 제조 방법을 나타낸 공정 단면도들이다.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 - -Explanation of symbols for the main parts of the drawings-
200 : 실리콘 기판 210 : 필드 산화막200: silicon substrate 210: field oxide film
220 : 게이트 산화막 230 : 폴리실리콘220: gate oxide film 230: polysilicon
240 : 텅스텐 실리사이드 250 : 층간 절연막240: tungsten silicide 250: interlayer insulating film
260 : 채널 영역 270 : 질화막260: channel region 270: nitride film
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