KR100493411B1 - 반도체 소자의 셀 플러그 형성방법 - Google Patents
반도체 소자의 셀 플러그 형성방법 Download PDFInfo
- Publication number
- KR100493411B1 KR100493411B1 KR10-2001-0032904A KR20010032904A KR100493411B1 KR 100493411 B1 KR100493411 B1 KR 100493411B1 KR 20010032904 A KR20010032904 A KR 20010032904A KR 100493411 B1 KR100493411 B1 KR 100493411B1
- Authority
- KR
- South Korea
- Prior art keywords
- cell plug
- insulating film
- interlayer insulating
- forming
- contact hole
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 2
- 239000010936 titanium Substances 0.000 description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 10
- 229910052719 titanium Inorganic materials 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000007517 polishing process Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
Claims (9)
- 삭제
- 반도체 기판상에 제 1 층간 절연막 및 제 2 층간 절연막을 차례로 형성하는 단계;상기 반도체 기판의 표면이 소정부분 노출되도록 상기 제 2 층간 절연막 및 제 1 층간 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계;상기 콘택홀에 상기 반도체 기판에 연결되는 제 1 셀 플러그를 형성하는 단계;상기 제 1 셀 플러그 표면에 실리사이드 콘택을 형성하는 단계;상기 콘택홀을 포함한 전면에 티타늄 질화막을 형성하는 단계;평탄화 공정으로 제 2 층간 절연막상의 티타늄 질화막을 제거하여 상기 콘택홀 내부에 제 2 셀 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 셀 플러그 형성방법.
- 삭제
- 제 2 항에 있어서, 상기 실리사이드 콘택은 화학기상증착법에 의한 인-시튜 티타늄 실리사이드 증착 공정으로 형성함을 특징으로 하는 반도체 소자의 셀 플러그형성방법.
- 제 2 항에 있어서, 상기 실리사이드 콘택은 물리기상증착법으로 금속막을 증착하고 열처리하여 상기 제 1 셀 플러그를 구성하는 물질과 금속막을 반응시키어 형성함을 특징으로 하는 반도체 소자의 셀 플러그 형성방법.
- 삭제
- 제 2 항에 있어서, 상기 제 1 셀 플러그는 단결정 실리콘으로 형성함을 특징으로 하는 반도체 소자의 셀 플러그 형성방법.
- 제 2 항에 있어서, 상기 제 1 셀 플러그는 다결정 실리콘으로 형성함을 특징으로 하는 반도체 소자의 셀 플러그 형성방법.
- 삭제
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0032904A KR100493411B1 (ko) | 2001-06-12 | 2001-06-12 | 반도체 소자의 셀 플러그 형성방법 |
JP2001288240A JP2003007820A (ja) | 2001-06-12 | 2001-09-21 | 半導体素子のプラグ製造方法 |
US10/166,685 US6667228B2 (en) | 2001-06-12 | 2002-06-12 | Method for fabricating cell plugs of semiconductor device |
US10/697,305 US6917111B2 (en) | 2001-06-12 | 2003-10-31 | Semiconductor device having cell plugs |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0032904A KR100493411B1 (ko) | 2001-06-12 | 2001-06-12 | 반도체 소자의 셀 플러그 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020094977A KR20020094977A (ko) | 2002-12-20 |
KR100493411B1 true KR100493411B1 (ko) | 2005-06-07 |
Family
ID=19710711
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2001-0032904A KR100493411B1 (ko) | 2001-06-12 | 2001-06-12 | 반도체 소자의 셀 플러그 형성방법 |
Country Status (3)
Country | Link |
---|---|
US (2) | US6667228B2 (ko) |
JP (1) | JP2003007820A (ko) |
KR (1) | KR100493411B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100791345B1 (ko) | 2006-10-02 | 2008-01-03 | 삼성전자주식회사 | 리세스된 구형 실리사이드 접촉부를 포함하는 반도체 소자및 그 제조 방법 |
KR100833430B1 (ko) * | 2006-04-25 | 2008-05-29 | 주식회사 하이닉스반도체 | 낸드 플래쉬 소자의 드레인 콘택플러그 형성방법 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6511879B1 (en) * | 2000-06-16 | 2003-01-28 | Micron Technology, Inc. | Interconnect line selectively isolated from an underlying contact plug |
KR100503519B1 (ko) * | 2003-01-22 | 2005-07-22 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
KR100616499B1 (ko) * | 2003-11-21 | 2006-08-28 | 주식회사 하이닉스반도체 | 반도체소자 제조 방법 |
US7407885B2 (en) * | 2005-05-11 | 2008-08-05 | Micron Technology, Inc. | Methods of forming electrically conductive plugs |
JP2007134705A (ja) * | 2005-11-07 | 2007-05-31 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
JP2007197302A (ja) * | 2005-12-28 | 2007-08-09 | Sumitomo Electric Ind Ltd | Iii族窒化物結晶の製造方法および製造装置 |
KR100805009B1 (ko) * | 2006-03-02 | 2008-02-20 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
US7410881B2 (en) | 2006-03-02 | 2008-08-12 | Hynix Semiconductor Inc. | Method of manufacturing flash memory device |
KR20140085657A (ko) | 2012-12-26 | 2014-07-08 | 에스케이하이닉스 주식회사 | 에어갭을 구비한 반도체장치 및 그 제조 방법 |
KR102001493B1 (ko) | 2013-04-16 | 2019-07-18 | 에스케이하이닉스 주식회사 | 에어갭을 구비한 반도체장치 및 그 제조 방법 |
KR102014950B1 (ko) | 2013-08-26 | 2019-08-28 | 에스케이하이닉스 주식회사 | 에어갭을 구비한 반도체장치 및 그 제조 방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990075619A (ko) * | 1998-03-23 | 1999-10-15 | 윤종용 | 반도체 장치의 커패시터 및 그 제조방법 |
KR20000027569A (ko) * | 1998-10-28 | 2000-05-15 | 김영환 | 반도체 소자의 제조 방법 |
KR20000043055A (ko) * | 1998-12-28 | 2000-07-15 | 김영환 | 반도체 소자의 비트 라인 형성 방법 |
US6153517A (en) * | 1999-03-12 | 2000-11-28 | Taiwan Semiconductor Manufacturing Company | Low resistance poly landing pad |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0618597B1 (en) * | 1993-03-31 | 1997-07-16 | Texas Instruments Incorporated | Lightly donor doped electrodes for high-dielectric-constant materials |
US6093615A (en) * | 1994-08-15 | 2000-07-25 | Micron Technology, Inc. | Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug |
US6171970B1 (en) * | 1998-01-27 | 2001-01-09 | Texas Instruments Incorporated | Method for forming high-density integrated circuit capacitors |
EP0977257A3 (en) | 1998-07-30 | 2003-09-10 | Texas Instruments Incorporated | Stacked capacitor DRAM cell and method of producing the same |
JP4807894B2 (ja) * | 1999-05-31 | 2011-11-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6511879B1 (en) * | 2000-06-16 | 2003-01-28 | Micron Technology, Inc. | Interconnect line selectively isolated from an underlying contact plug |
US6455424B1 (en) * | 2000-08-07 | 2002-09-24 | Micron Technology, Inc. | Selective cap layers over recessed polysilicon plugs |
-
2001
- 2001-06-12 KR KR10-2001-0032904A patent/KR100493411B1/ko active IP Right Grant
- 2001-09-21 JP JP2001288240A patent/JP2003007820A/ja active Pending
-
2002
- 2002-06-12 US US10/166,685 patent/US6667228B2/en not_active Expired - Lifetime
-
2003
- 2003-10-31 US US10/697,305 patent/US6917111B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990075619A (ko) * | 1998-03-23 | 1999-10-15 | 윤종용 | 반도체 장치의 커패시터 및 그 제조방법 |
KR20000027569A (ko) * | 1998-10-28 | 2000-05-15 | 김영환 | 반도체 소자의 제조 방법 |
KR20000043055A (ko) * | 1998-12-28 | 2000-07-15 | 김영환 | 반도체 소자의 비트 라인 형성 방법 |
US6153517A (en) * | 1999-03-12 | 2000-11-28 | Taiwan Semiconductor Manufacturing Company | Low resistance poly landing pad |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100833430B1 (ko) * | 2006-04-25 | 2008-05-29 | 주식회사 하이닉스반도체 | 낸드 플래쉬 소자의 드레인 콘택플러그 형성방법 |
KR100791345B1 (ko) | 2006-10-02 | 2008-01-03 | 삼성전자주식회사 | 리세스된 구형 실리사이드 접촉부를 포함하는 반도체 소자및 그 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
JP2003007820A (ja) | 2003-01-10 |
KR20020094977A (ko) | 2002-12-20 |
US20020186601A1 (en) | 2002-12-12 |
US6917111B2 (en) | 2005-07-12 |
US6667228B2 (en) | 2003-12-23 |
US20040056353A1 (en) | 2004-03-25 |
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