KR100493021B1 - 반도체 메모리 장치 및 그의 제조방법 - Google Patents
반도체 메모리 장치 및 그의 제조방법 Download PDFInfo
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- KR100493021B1 KR100493021B1 KR10-2002-0040091A KR20020040091A KR100493021B1 KR 100493021 B1 KR100493021 B1 KR 100493021B1 KR 20020040091 A KR20020040091 A KR 20020040091A KR 100493021 B1 KR100493021 B1 KR 100493021B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 42
- 230000002093 peripheral effect Effects 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 238000002955 isolation Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- NCMAYWHYXSWFGB-UHFFFAOYSA-N [Si].[N+][O-] Chemical compound [Si].[N+][O-] NCMAYWHYXSWFGB-UHFFFAOYSA-N 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims description 2
- 238000005192 partition Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (16)
- 반도체 기판 상에 소정의 구획을 형성하면서 메모리 소자들이 형성된 셀 영역과 상기 셀 영역을 둘러싸고 형성된 주변회로 영역을 포함하는 반도체 메모리 장치에 있어서,상기 셀 영역에 형성되어 메모리 소자 역할을 하며, 게이트와 상기 게이트의 양측으로 형성된 소스/드레인 및 제1두께를 가진 제1게이트 절연막을 포함하는 복수의 셀 트랜지스터;상기 주변회로 영역에 형성되어 제1두께를 가진 제1게이트 절연막을 포함하는 복수의 코아 트랜지스터; 및상기 셀 영역의 게이트에 네거티브 바이어스(negative bias)를 인가하며 상기 복수의 셀 트랜지스터 및 상기 복수의 코아 트랜지스터에 대해 균일한 문턱전압을 가지면서 상기 셀 영역과 인접한 상기 주변회로 영역에 배치된 제2두께를 가진 제2게이트 절연막을 포함하는 복수의 게이트 네거티브 바이어스용(negative bias) 트랜지스터를 포함하는 것을 특징으로 하는 반도체 메모리 장치.
- 제1항에 있어서, 상기 게이트 네거티브 바이어스용 트랜지스터(gate negative-bias transistor)는 상기 셀 트랜지스터(Cell transistor)의 게이트와 전기적으로 연결된 것을 특징으로 하는 반도체 메모리 장치.
- 제1항에 있어서, 상기 제1게이트 절연막은 상기 제2절연막의 두께보다 더 두꺼운 것을 특징으로 하는 반도체 메모리 장치.
- 제3항에 있어서, 상기 제1게이트 절연막 및 상기 제2게이트 절연막은 실리콘 산화막인 것을 특징으로 하는 반도체 메모리 장치.
- 제4항에 있어서, 상기 제1게이트 절연막은 2단계 산화법으로 형성되는 것을 특징으로 하는 반도체 메모리 장치.
- a) 소정의 소자분리법으로 소자분리용 절연막을 형성하여 셀 영역과 주변회로 영역의 소자형성 영역 및 게이트 네거티브 바이어스(negative bias) 영역을 정의하는 단계;b) 상기 셀 영역과 상기 주변회로 영역의 상기 소자형성 영역에 제1 두께의 제1게이트 절연막을 형성하고, 상기 게이트 네거티브 바이어스 영역에 상기 제1게이트 절연막에 의한 문턱전압에 대해 균일한 문턱전압을 갖도록 제2두께의 제2게이트 절연막을 형성하는 단계; 및c) 상기 소자형성 영역에 게이트 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 메모리 장치의 제조방법.
- 제6항에 있어서, 상기 소자분리용 절연막은 실리콘 산화막인 것을 특징으로 하는 반도체 메모리 장치의 제조방법.
- 제6항에 있어서, 상기 b)단계는,상기 소자 형성영역을 노출시키는 단계;상기 노출된 소자형성 영역에 상기 반도체 기판을 산화시켜 제1절연막을 형성하는 단계;상기 반도체 기판 상에 포토 레지스트를 형성하는 단계;상기 포토 레지스트에 정렬/노광으로 상기 게이트 네거티브 바이어스 영역이 노출되도록 패턴을 형성하는 단계;상기 패턴닝된 포토 레지스트를 마스크로 이용하여 소정의 식각법으로 상기 게이트 네거티브 바이어스 영역에 형성된 제1절연막을 제거하는 단계; 및상기 반도체 기판의 소자형성 영역과 상기 네거티브 바이어스 영역에 제2절연막을 형성하여 상기 셀 영역과 상기 주변회로 영역에는 제1게이트 절연막을 형성하고, 상기 게이트 네거티브 바이어스 영역에는 제2게이트 절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 메모리 장치의 제조방법.
- 제8항에 있어서, 상기 제1절연막은 실리콘 산화막과 실리콘 질소 산화막(Oxynitride) 중 어느 하나인 것을 특징으로 하는 반도체 메모리 장치의 제조방법.
- 제9항에 있어서, 상기 제1절연막은 열적 산화법(thermal oxidation)으로 형성되는 것을 특징으로 하는 반도체 메모리 장치의 제조방법.
- 제8항에 있어서, 상기 식각법은 식각용액을 이용한 습식 식각법인 것을 특징으로 하는 반도체 메모리 장치의 제조방법.
- 제11항에 있어서, 상기 식각용액은 산화막을 식각할 수 있는 불산(HF)을 포함하는 것을 특징으로 하는 반도체 메모리 장치의 제조방법.
- 제8항에 있어서, 상기 제2절연막은 실리콘 산화막(SiO2)과 실리콘 질소 산화막(SiON) 중 어느 하나인 것을 특징으로 하는 반도체 메모리 장치의 제조방법.
- 제6항에 있어서, 상기 c)단계는,상기 반도체 기판 전면에 게이트 도전막을 형성하는 단계;상기 게이트 도전막 상에 게이트 패턴을 가진 포토 레지스트를 형성하는 단계;상기 포토 레지스트를 마스크로 이용하여 건식식각법으로 상기 게이트 도전막에 게이트 패턴을 전사하는 단계를 포함하는 것을 특징으로 하는 반도체 메모리 정치의 제조방법.
- 제14항에 있어서, 상기 게이트 도전막은 불순물이 도핑된 도전성의 폴리 실리콘인 것을 특징으로 하는 반도체 메모리 정치의 제조방법.
- 제14항에 있어서, 상기 게이트 도전막은 폴리 실리콘과 금속 실리사이드막으로 구성된 것을 특징으로 하는 반도체 메모리 장치의 제조방법.
Priority Applications (3)
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KR10-2002-0040091A KR100493021B1 (ko) | 2002-07-10 | 2002-07-10 | 반도체 메모리 장치 및 그의 제조방법 |
US10/421,240 US6867445B2 (en) | 2002-07-10 | 2003-04-23 | Semiconductor memory devices including different thickness dielectric layers for the cell transistors and refresh transistors thereof |
US11/042,495 US7498220B2 (en) | 2002-07-10 | 2005-01-25 | Methods of fabricating semiconductor memory devices including different dielectric layers for the cell transistors and refresh transistors thereof |
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Cited By (1)
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KR101844058B1 (ko) | 2012-02-01 | 2018-03-30 | 에스케이하이닉스 주식회사 | 복층 금속 콘택을 포함하는 반도체 소자 |
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US7976941B2 (en) | 1999-08-31 | 2011-07-12 | Momentive Performance Materials Inc. | Boron nitride particles of spherical geometry and process for making thereof |
US6713088B2 (en) * | 1999-08-31 | 2004-03-30 | General Electric Company | Low viscosity filler composition of boron nitride particles of spherical geometry and process |
US7445797B2 (en) * | 2005-03-14 | 2008-11-04 | Momentive Performance Materials Inc. | Enhanced boron nitride composition and polymer-based compositions made therewith |
US6764975B1 (en) * | 2000-11-28 | 2004-07-20 | Saint-Gobain Ceramics & Plastics, Inc. | Method for making high thermal diffusivity boron nitride powders |
CN100398589C (zh) * | 2001-04-30 | 2008-07-02 | 圣戈本陶瓷及塑料股份有限公司 | 聚合物加工用助剂和加工方法 |
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KR100442885B1 (ko) * | 2002-11-01 | 2004-08-02 | 삼성전자주식회사 | 반도체 소자의 다중 두께 게이트 유전층 제조 방법 |
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Also Published As
Publication number | Publication date |
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US6867445B2 (en) | 2005-03-15 |
US7498220B2 (en) | 2009-03-03 |
US20050158951A1 (en) | 2005-07-21 |
KR20040005514A (ko) | 2004-01-16 |
US20040007764A1 (en) | 2004-01-15 |
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