KR100472859B1 - Method of forming a metal line in a semiconductor device - Google Patents

Method of forming a metal line in a semiconductor device Download PDF

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KR100472859B1
KR100472859B1 KR10-2002-0085495A KR20020085495A KR100472859B1 KR 100472859 B1 KR100472859 B1 KR 100472859B1 KR 20020085495 A KR20020085495 A KR 20020085495A KR 100472859 B1 KR100472859 B1 KR 100472859B1
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forming
layer
plating
copper layer
film formed
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KR10-2002-0085495A
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KR20040058973A (en
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표성규
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 듀얼 다마신 패턴상에 확산 방지막 및 시드층을 형성하고, 전기도금법 또는 무전해 도금법을 이용하여 구리층을 매립한 후 Cl이 없는 전해질을 이용한 전해 에칭과 Cl이 없는 전해질을 이용한 전기도금법 또는 무전해 도금법을 이용하여 구리층을 재매립함으로써 구리층에 생성된 마이크로 및 매크로 결함등을 제거할 뿐만 아니라 구리층 표면에 존재 가능한 폴리머등의 불순물등을 효과적으로 제거하여 소자의 수율을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법이 제시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein a diffusion barrier film and a seed layer are formed on a dual damascene pattern, and a copper layer is embedded using an electroless plating method or an electroless plating method, and then an electrolyte without Cl is used. Refilling the copper layer by electroplating or electroless plating using an electrolytic etch and Cl-free electrolyte eliminates micro and macro defects generated in the copper layer, as well as impurities such as polymers that may be present on the surface of the copper layer. Provided is a method of forming a metal wiring of a semiconductor device capable of effectively removing the component and improving the yield of the device.

Description

반도체 소자의 금속 배선 형성 방법{Method of forming a metal line in a semiconductor device} Method of forming a metal line in a semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 구리 전기도금 공정에서 치명적인 결함으로 작용하는 보이드 및 피트(pit)등의 마이크로 및 매크로 결함등을 제거할 뿐만 아니라 구리층 표면에 존재 가능한 폴리머등의 불순물등을 효과적으로 제거할 수 있어 소자의 수율을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for forming metal wirings in semiconductor devices. In particular, the present invention relates to polymers capable of removing micro and macro defects, such as voids and pits, which act as fatal defects in copper electroplating processes, as well as polymers that can exist on the surface of copper layers The present invention relates to a method for forming a metal wiring of a semiconductor device capable of effectively removing impurities such as the like and improving the yield of the device.

구리 배선 공정의 필요성이 대두되기 시작한 1990년을 전후해서 도금법 (plating), PVD법, CVD법 등에 대한 연구가 경쟁적으로 진행되고 있다. 도금법에는 무전해도금법(electroless plating)과 전기도금법(electroplating)이 있는데, 무전해 도금법은 높은 애스펙트비(aspect ratio)에서도 우수한 갭필(gap fill) 특성과 고속 성장을 나타내지만, 그레인 사이즈가 작아 EM에 대한 내성이 낮고 화학 반응도 복잡하여 제어가 어렵다. 이에 비해 전기도금법은 성장 속도가 빠를 뿐만 아니라 화학 반응성이 비교적 간단하고 취급이 쉬우며 그레인 사이즈가 크고 양호한 막질을 얻을 수 있으므로 EM에 대한 내성이 우수하다. 그러나 전기도금법을 이용한 구리층 매립 공정은 소자 특성에 영향을 미치는 결함(defect)을 내포하고 있어 이의 감소를 위한 노력이 개진되고 있다. 그러면, 전기도금법에 의한 구리층 매립 공정에서 발생되는 주요 결함을 설명하면 다음과 같다.Around 1990, when the need for the copper wiring process began to emerge, research on plating, PVD, CVD, etc., has been competitively conducted. There are two types of plating methods, electroless plating and electroplating. Electroless plating shows excellent gap fill characteristics and fast growth even at high aspect ratios. It is difficult to control because of its low resistance to chemical reactions. On the other hand, the electroplating method is not only fast growing, but also has a relatively simple chemical reactivity, easy handling, large grain size, and good film quality, thereby providing excellent resistance to EM. However, the copper layer embedding process using the electroplating method contains a defect that affects the device characteristics, and efforts to reduce it have been made. Then, the main defects generated in the copper layer embedding process by the electroplating method is as follows.

먼저, 전기도금법으로 구리층을 매립하면 비아 및 트렌치에서 보이드가 발생하게 되는데, 이는 균일한 시드층의 증착을 필요로 하게 되며, 전기도금법의 화학 조성 및 인가 전류에 의하여 영향을 받는다. 또한, 패턴 밀도에 따라서 전기 도금막의 두께가 심하게 다르게 나타나는 과다 도금(overplating)에 의한 돌기(protrusion)가 발생되는데, 이는 도금액 속에 첨가하는 첨가제에 따라 큰 영향을 받으며, 후속 CMP 공정에 큰 문제를 발생시킨다. 그리고, 여러가지 복합적인 원인들에 의해 발생하는 피트(pit)가 배선 라인에 발생되면 소자의 불량 원인이 된다.First, when the copper layer is buried by the electroplating method, voids are generated in the vias and the trenches, which requires uniform deposition of the seed layer and is affected by the chemical composition and the applied current of the electroplating method. In addition, protrusion occurs due to overplating, in which the thickness of the electroplating film varies greatly depending on the pattern density, which is greatly influenced by the additives added to the plating solution, and causes a large problem in subsequent CMP processes. Let's do it. In addition, if a pit generated by various complex causes is generated in the wiring line, it causes a failure of the device.

본 발명의 목적은 전기도금법으로 구리층을 형성할 때 발생하여 치명적인 결함으로 작용하는 보이드 및 피트등의 결함을 제거할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 있다. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of eliminating defects such as voids and pits that occur when forming a copper layer by electroplating and act as fatal defects.

본 발명의 다른 목적은 보이드 및 피트등의 결함을 Cl이 없는 전해질을 이용한 전해 에칭 및 구리층 재형성에 의해 제거하는 반도체 소자의 금속 배선 형성 방법을 제공하는데 있다. Another object of the present invention is to provide a method for forming metal wirings of a semiconductor device in which defects such as voids and pits are removed by electrolytic etching and copper layer reforming using an electrolyte without Cl.

본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 소정의 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성한 후 상기 층간 절연막의 소정 영역에 다마신 패턴을 형성하는 단계와, 상기 다마신 패턴을 포함한 전체 구조 상부에 확산 방지막 및 시드층을 형성한 후 제 1 구리층을 형성하는 단계와, Cl이 없는 전해질을 이용한 전해 에칭 공정을 실시하여 상기 제 1 구리층을 식각하는 단계와, 상기 Cl이 없는 전해질을 이용하여 전체 구조 상부에 제 2 구리층을 형성하는 단계와, 상기 제 2 및 제 1 구리층, 시드층 및 확산 방지막을 연마하여 구리 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In the method of forming a metal wiring of a semiconductor device according to the present invention, forming an interlayer insulating film on a semiconductor substrate having a predetermined structure, and then forming a damascene pattern in a predetermined region of the interlayer insulating film, and including the entire damascene pattern. Forming a first copper layer after forming a diffusion barrier layer and a seed layer on the structure, etching the first copper layer by performing an electrolytic etching process using an electrolyte without Cl, and the electrolyte without Cl Forming a second copper layer on the entire structure using the; and polishing the second and the first copper layer, the seed layer and the diffusion barrier layer to form a copper wiring.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예는 본 발명의 개시가 완전하도록 하며, 이 기술 분야에서 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한, 도면상에서 동일 부호는 동일 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.

도 1(a) 내지 도 1(e)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (e) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.

도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(101) 상부에 제 1 식각 정지막(102)을 형성하고 제 1 층간 절연막(103)을 형성한다. 제 1 층간 절연막(103) 및 제 1 식각 정지막(102)의 소정 영역을 식각하여 반도체 기판(101)을 노출시킨다. 노출된 반도체 기판(101)을 포함한 전체 구조 상부에 제 1 확산 방지막(104) 및 제 1 구리층(105)을 형성한 후 연마 공정을 실시하여 하부 금속 배선을 형성한다. 이때, 제 1 구리층(105) 대신에 텅스텐 또는 알루미늄을 형성할 수도 있는데, 텅스텐 또는 알루미늄을 형성할 경우 식각 공정에 의한 패터닝으로 형성할 수도 있다. 전체 구조 상부에 제 2 식각 정지막(106), 제 2 층간 절연막(107), 제 3 식각 정지막(108), 제 3 층간 절연막(109) 및 하드 마스크층(110)을 순차적으로 형성한다. 하드 마스크층(110) 및 제 3 층간 절연막(109)의 소정 영역을 식각하여 트렌치를 형성한 후 제 2 층간 절연막(107) 및 제 2 식각 정지막(106)의 소정 영역을 식각하여 비아홀을 형성한다. 이때, 비아홀을 먼저 형성하고 트렌치를 나중에 형성할 수도 있다. 이에 의해 트렌치 및 비아홀로 구성된 듀얼 다마신 패턴이 형성된다.Referring to FIG. 1A, a first etch stop layer 102 is formed on a semiconductor substrate 101 on which a predetermined structure is formed, and a first interlayer insulating layer 103 is formed. Predetermined regions of the first interlayer insulating layer 103 and the first etch stop layer 102 are etched to expose the semiconductor substrate 101. After forming the first diffusion barrier film 104 and the first copper layer 105 on the entire structure including the exposed semiconductor substrate 101, a polishing process is performed to form a lower metal wiring. In this case, tungsten or aluminum may be formed instead of the first copper layer 105, and when tungsten or aluminum is formed, it may be formed by patterning by an etching process. The second etch stop layer 106, the second interlayer insulating layer 107, the third etch stop layer 108, the third interlayer insulating layer 109 and the hard mask layer 110 are sequentially formed on the entire structure. A trench is formed by etching a predetermined region of the hard mask layer 110 and the third interlayer insulating layer 109, and then a via hole is formed by etching a predetermined region of the second interlayer insulating layer 107 and the second etch stop layer 106. do. In this case, the via hole may be formed first and the trench may be formed later. As a result, a dual damascene pattern composed of trenches and via holes is formed.

상기에서 제 1, 제 2 및 제 3 층간 절연막(103, 107 및 109)은 각각 저유전율을 갖는 절연막을 이용하여 형성한다. 그리고, 제 1 확산 방지막(104)은 이온화(ionized) PVD 방법에 의해 형성된 TiN막, CVD 방법에 의해 형성된 TiN막, MOCVD 방법에 의해 형성된 TiN막, 이온화(ionized) PVD 방법에 의해 형성된 Ta막, 이온화(ionized) PVD 방법에 의해 형성된 TaN막, CVD 방법에 의해 형성된 WN막, PVD 방법 또는 CVD 방법에 의해 형성된 TiAlN막, TiSiN막 및 TaSiN막 중 어느 하나를 이용하여 형성한다.In the above, the first, second and third interlayer insulating films 103, 107 and 109 are formed using insulating films having low dielectric constants, respectively. The first diffusion barrier film 104 includes a TiN film formed by an ionized PVD method, a TiN film formed by a CVD method, a TiN film formed by a MOCVD method, a Ta film formed by an ionized PVD method, It is formed using any one of a TaN film formed by an ionized PVD method, a WN film formed by a CVD method, a TiAlN film, a TiSiN film, and a TaSiN film formed by a PVD method or a CVD method.

도 1(b)를 참조하면, 클리닝 공정을 실시하고, 듀얼 다마신 패턴을 포함한 전체 구조 상부에 제 2 확산 방지막(111) 및 시드층(112)을 형성한 후 전기 도금법 또는 무전해 도금법을 이용하여 제 2 구리층(113)을 형성한다. 그런데, 이러한 방법으로 형성된 제 2 구리층(113)에는 피트 또는 보이드등의 결함(114)이 생성되게 된다.Referring to FIG. 1B, a cleaning process is performed, and a second diffusion barrier layer 111 and a seed layer 112 are formed on the entire structure including the dual damascene pattern, and then electroplating or electroless plating is used. Thus, the second copper layer 113 is formed. However, defects 114 such as pits or voids are generated in the second copper layer 113 formed in this manner.

상기에서 클리닝 공정은 하부 금속 배선이 텅스텐 또는 알루미늄으로 형성되었을 경우 RF 플라즈마를 이용하여 실시하고, 하부 금속 배선이 구리로 형성되었을 경우 리액티브 클리닝 방법을 이용하여 실시한다. 그리고, 제 2 확산 방지막(111)은 이온화(ionized) PVD 방법에 의해 형성된 TiN막, CVD 방법에 의해 형성된 TiN막, MOCVD 방법에 의해 형성된 TiN막, 이온화(ionized) PVD 방법에 의해 형성된 Ta막, 이온화(ionized) PVD 방법에 의해 형성된 TaN막, CVD 방법에 의해 형성된 WN막, PVD 방법 또는 CVD 방법에 의해 형성된 TiAlN막, TiSiN막 및 TaSiN막 중 어느 하나를 이용하여 형성한다. 또한, 시드층(112)은 Cu, Ni, Mo, Pt, Ti, Al등을 PVD 방법, CVD 방법 또는 ALD 방법을 이용하여 50∼500Å의 두께로 형성한다. 전기도금법은 1분 내지 48시간 동안 실시하며, 펄스 플레이팅(pulse plating), 멀티플(multiple) DC 플레이팅, 포워드(forward) 펄스 플레이팅 등을 실시할 수 있고, 멀티플 DC 플레이팅을 실시하는 경우 0.1㎃∼5A의 웨팅 스테이지 커런트 (wetting stage current)를 포함하는 다단계 플레이팅 방법을 실시할 수 있다.The cleaning process is performed by using RF plasma when the lower metal wiring is formed of tungsten or aluminum, and using a reactive cleaning method when the lower metal wiring is formed of copper. The second diffusion barrier layer 111 is a TiN film formed by an ionized PVD method, a TiN film formed by a CVD method, a TiN film formed by a MOCVD method, a Ta film formed by an ionized PVD method, It is formed using any one of a TaN film formed by an ionized PVD method, a WN film formed by a CVD method, a TiAlN film, a TiSiN film, and a TaSiN film formed by a PVD method or a CVD method. In addition, the seed layer 112 is formed of Cu, Ni, Mo, Pt, Ti, Al, or the like to have a thickness of 50 to 500 kV using a PVD method, a CVD method, or an ALD method. The electroplating method is performed for 1 minute to 48 hours, and may be pulse plating, multiple DC plating, forward pulse plating, or the like when multiple DC plating is performed. A multistage plating method including a wetting stage current of 0.1 mA to 5 A can be performed.

도 1(c)를 참조하면, Cl이 없는 전해질(electrolyte), 즉 전기도금법에서 사용되는 액셀레이터(accelator), 서프레서(suppressor), 레벨러(leveler) 등의 폴리머가 없는 전해질을 이용한 전해 에칭을 실시한다. 이에 의해 제 2 구리층(113)에 생성된 피트, 보이드 등의 결함(114)은 더욱 넓어져 미세 피트까지도 매립에 어려움이 없게 된다. 한편, 전해 에칭의 한 방법으로서 리버스 플레이팅(reverse plating)을 실시할 수 있으며, 전해 에칭 용액으로는 전기도금법을 실시할 때 포함되는 폴리머등의 첨가제를 전혀 첨가하지 않은 H2SO4와 CuSO4가 혼합된 전해질을 이용하며, 이때 H2SO4와 CuSO4의 비율은 1:99∼99:1 정도로 한다.Referring to FIG. 1C, an electrolytic etching is performed using an electrolyte without Cl, that is, an electrolyte without a polymer such as an accelerator, a suppressor, and a leveler used in the electroplating method. do. As a result, defects 114 such as pits and voids generated in the second copper layer 113 are further widened so that even fine pits are not difficult to be embedded. On the other hand, reverse plating may be performed as a method of electrolytic etching, and as an electrolytic etching solution, H 2 SO 4 and CuSO 4 containing no additives such as polymers included in the electroplating method are added. Mixed electrolyte is used, wherein the ratio of H 2 SO 4 to CuSO 4 is 1:99 to 99: 1.

도 1(d)를 참조하면, Cl이 없는 전해질, 즉 액셀레이터(accelator), 서프레서(suppressor), 레벨러(leveler) 등의 폴리머가 없는 전해질을 이용한 전기도금법 또는 무전해 도금법을 이용하여 전체 구조 상부에 제 3 구리층(115)을 형성한다. 이에 의해 제 2 구리층(113) 표면에 형성된 보이드 또는 피트 홀 등의 마이크로(micro) 및 매크로(macro) 결함, swirl-LOP(Line Of Pit)를 재매립할 뿐만 아니라 제 2 구리층(113)의 표면에 존재할 수 있는 폴리머등의 불순물등을 효과적으로 제거하여 소자에 치명적인 결함을 제거한다. 이때, 전기도금 용액으로는 전기도금법을 실시할 때 포함되는 폴리머등의 첨가제를 전혀 첨가하지 않은 H2SO4와 CuSO4가 혼합된 전해질을 이용하며, 이때 H2SO4와 CuSO4의 비율은 1:99∼99:1 정도로 한다.Referring to FIG. 1 (d), the upper portion of the entire structure is formed by using an electroless plating method or an electroless plating method using an electrolyte without Cl, that is, an electrolyte without a polymer such as an accelerator, a suppressor, a leveler, or the like. The third copper layer 115 is formed on the substrate. As a result, micro and macro defects, such as voids or pit holes, and swirl-LOP (Line Of Pit) formed on the surface of the second copper layer 113 may be refilled, and the second copper layer 113 may be refilled. It effectively removes impurities such as polymers that may exist on the surface of the chip to remove the fatal defects in the device. At this time, the electroplating solution as is and using the polymers of the additive with a H 2 SO 4 and CuSO 4 is not added at all mixing the electrolyte included when performing the electroplating method, wherein the ratio of H 2 SO 4 and CuSO 4 is 1:99 to 99: 1.

도 1(e)는 CMP 공정을 실시하여 상부 금속 배선을 형성한 상태의 단면도이다.FIG. 1E is a cross-sectional view of a state in which an upper metal wiring is formed by performing a CMP process.

상술한 바와 같이 본 발명에 의하면 듀얼 다마신 패턴상에 확산 방지막 및 시드층을 형성하고, 전기도금법 또는 무전해 도금법을 이용하여 구리층을 매립한 후 Cl이 없는 전해질을 이용한 전해 에칭과 Cl이 없는 전해질을 이용한 전기도금법 또는 무전해 도금법을 이용하여 구리층을 재매립함으로써 구리층에 생성된 보이드 및 피트(pit)등의 마이크로 및 매크로 결함등을 제거할 뿐만 아니라 구리층 표면에 존재 가능한 폴리머등의 불순물등을 효과적으로 제거하여 소자의 수율을 향상시킬 수 있다.As described above, according to the present invention, a diffusion barrier layer and a seed layer are formed on the dual damascene pattern, and the copper layer is embedded using an electroplating method or an electroless plating method. Refilling the copper layer using electroplating or electroless plating using an electrolyte removes micro and macro defects such as voids and pits generated in the copper layer as well as polymers that may be present on the surface of the copper layer. Impurities can be effectively removed to improve the yield of the device.

도 1(a) 내지 도 1(e)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (e) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101 : 반도체 기판 102 : 제 1 확산 방지막101 semiconductor substrate 102 first diffusion barrier film

103 : 제 1 층간 절연막 104 : 제 2 확산 방지막103: first interlayer insulating film 104: second diffusion barrier film

105 : 제 1 구리층 106 : 제 3 확산 방지막105: first copper layer 106: third diffusion barrier film

107 : 제 2 층간 절연막 108 : 식각 정지막107: Second interlayer insulating film 108: Etch stop film

109 : 제 3 층간 절연막 110 : 하드 마스크층109: third interlayer insulating film 110: hard mask layer

111 : 제 4 확산 방지막 112 : 시드층111: fourth diffusion barrier film 112: seed layer

113 : 제 2 구리층 114 : 결함113: second copper layer 114: defect

115 : 제 3 구리층115: third copper layer

Claims (11)

소정의 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성한 후 상기 층간 절연막의 소정 영역에 다마신 패턴을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate on which a predetermined structure is formed, and then forming a damascene pattern in a predetermined region of the interlayer insulating film; 상기 다마신 패턴을 포함한 전체 구조 상부에 확산 방지막 및 시드층을 형성한 후 제 1 구리층을 형성하는 단계;Forming a first copper layer after forming a diffusion barrier layer and a seed layer on the entire structure including the damascene pattern; Cl이 없는 전해질을 이용한 전해 에칭 공정을 실시하여 상기 제 1 구리층을 식각하는 단계;Etching the first copper layer by performing an electrolytic etching process using an electrolyte free of Cl; 상기 Cl이 없는 전해질을 이용하여 전체 구조 상부에 제 2 구리층을 형성하는 단계; 및Forming a second copper layer on the entire structure by using the electrolyte without Cl; And 상기 제 2 및 제 1 구리층, 시드층 및 확산 방지막을 연마하여 구리 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And forming a copper wiring by polishing the second and first copper layers, the seed layer, and the diffusion barrier layer. 제 1 항에 있어서, 상기 확산 방지막은 이온화(ionized) PVD 방법에 의해 형성된 TiN막, CVD 방법에 의해 형성된 TiN막, MOCVD 방법에 의해 형성된 TiN막, 이온화(ionized) PVD 방법에 의해 형성된 Ta막, 이온화(ionized) PVD 방법에 의해 형성된 TaN막, CVD 방법에 의해 형성된 WN막, PVD 방법 또는 CVD 방법에 의해 형성된 TiAlN막, TiSiN막 및 TaSiN막 중 어느 하나를 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The diffusion barrier is a TiN film formed by an ionized PVD method, a TiN film formed by a CVD method, a TiN film formed by a MOCVD method, a Ta film formed by an ionized PVD method. A semiconductor device formed using any one of a TaN film formed by an ionized PVD method, a WN film formed by a CVD method, a TiAlN film, a TiSiN film, and a TaSiN film formed by a PVD method or a CVD method. Method of forming metal wiring. 제 1 항에 있어서, 상기 시드층은 Cu, Ni, Mo, Pt, Ti, Al중 어느 하나를 PVD 방법, CVD 방법 또는 ALD 방법을 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the seed layer is formed of any one of Cu, Ni, Mo, Pt, Ti, and Al using a PVD method, a CVD method, or an ALD method. 제 1 항에 있어서, 상기 제 1 및 제 2 구리층은 전기도금법 또는 무전해 도금법을 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the first and second copper layers are formed using an electroplating method or an electroless plating method. 제 4 항에 있어서, 상기 전기도금법은 1분 내지 48시간 동안 실시하며, 펄스 플레이팅(pulse plating), 멀티플(multiple) DC 플레이팅, 포워드(forward) 펄스 플레이팅중 어느 하나로 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 4, wherein the electroplating method is performed for 1 minute to 48 hours, and any one of pulse plating, multiple DC plating, and forward pulse plating is performed. A metal wiring formation method of a semiconductor element. 제 5 항에 있어서, 상기 멀티플 DC 플레이팅은 0.1㎃ 내지 5A의 웨팅 스테이지 커런트를 포함하는 다단계 플레이팅 방법으로 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 5, wherein the multiple DC plating is performed by a multi-step plating method including a wetting stage current of 0.1 kV to 5 A. 7. 제 1 항에 있어서, 상기 전해 에칭 공정은 리버스 플레이팅으로 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the electrolytic etching step is performed by reverse plating. 제 1 항에 있어서, 상기 전해 에칭 공정은 전기도금법을 실시할 때 포함되는 폴리머등의 첨가제가 전혀 첨가되지 않은 H2SO4와 CuSO4가 혼합된 전해질을 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The semiconductor device according to claim 1, wherein the electrolytic etching process is performed using an electrolyte in which H 2 SO 4 and CuSO 4 are mixed with no additives such as a polymer included in the electroplating method. Method of forming metal wiring. 제 8 항에 있어서, 상기 H2SO4와 CuSO4는 1:99 내지 99:1의 비율료 혼합된 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 8, wherein the H 2 SO 4 and CuSO 4 are mixed in a ratio of 1:99 to 99: 1. 제 1 항에 있어서, 상기 제 2 구리층은 전기도금법을 실시할 때 포함되는 폴리머등의 첨가제를 전혀 첨가하지 않은 H2SO4와 CuSO4가 혼합된 전해질을 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The semiconductor of claim 1, wherein the second copper layer is formed using an electrolyte in which H 2 SO 4 and CuSO 4 are mixed without any additives such as a polymer included in the electroplating method. Method for forming metal wiring of the device. 제 10 항에 있어서, 상기 H2SO4와 CuSO4는 1:99 내지 99:1의 비율로 혼합된 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 10, wherein the H 2 SO 4 and CuSO 4 are mixed in a ratio of 1:99 to 99: 1.
KR10-2002-0085495A 2002-12-27 2002-12-27 Method of forming a metal line in a semiconductor device KR100472859B1 (en)

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