KR100464938B1 - A method for forming capacitor using polysilicon plug structure in semiconductor device - Google Patents
A method for forming capacitor using polysilicon plug structure in semiconductor device Download PDFInfo
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- KR100464938B1 KR100464938B1 KR10-2000-0080589A KR20000080589A KR100464938B1 KR 100464938 B1 KR100464938 B1 KR 100464938B1 KR 20000080589 A KR20000080589 A KR 20000080589A KR 100464938 B1 KR100464938 B1 KR 100464938B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
Abstract
본 발명은 반도체 제조 기술에 관한 것으로, 특히 금속 하부전극과 반도체 기판의 전기적인 콘택을 위해 폴리실리콘 플러그 구조를 사용한 반도체 소자의 캐패시터 형성방법을 가진 캐패시터 형성방법에 관한 것이며, 금속 하부전극 및 유전체 박막으로부터 캐패시터 하부 구조로 산소가 확산되는 것을 줄일 수 있는 반도체 소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다. 본 발명에서는 캐패시터의 하부금속전극을 형성함에 있어서, 우선 1차로 PVD 금속막을 증착하고, 그 상부에 2차로 CVD 금속막을 증착한다. 폴리실리콘 플러그 구조쪽에 배치된 PVD 금속막은 박막 내부에 산소를 거의 포함하지 않을 뿐만 아니라, CVD 금속막에 비해 산소 통과(penetration) 방지 특성이 우수하기 때문에 CVD 금속막 및 그 상부의 유전체 박막으로부터 캐패시터 하부 구조로 산소가 확산되는 것을 줄일 수 있다. 한편, CVD 금속막 내에 존재하는 산소가 하부 구조로 확산되지 않고 오히려 유전체 박막 쪽으로 확산되어 산소 공급원으로 작용함으로써 유전체 박막의 산소 화학량론을 유지하는데 도움을 줄 수 있다. 본 발명에서 PVD 금속막만을 사용하지 않고 CVD와 혼용하는 이유는 이너 실린더 캐패시터와 같이 3차원 구조를 가지는 캐패시터에서 PVD 금속막만으로는 충분한 스텝 커버리지를 얻을 수 없기 때문이며, PVD 금속막이 후속 CVD 금속막 증착시 씨드(seed)층 역할을 수행하여 CVD 금속막의 스텝 커버리지를 더욱 좋게 만든다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a capacitor forming method having a method of forming a capacitor of a semiconductor device using a polysilicon plug structure for electrical contact between a metal bottom electrode and a semiconductor substrate. It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device that can reduce the diffusion of oxygen from the capacitor structure to the capacitor. In the present invention, in forming the lower metal electrode of the capacitor, first, a PVD metal film is first deposited, and a CVD metal film is secondly deposited thereon. The PVD metal film disposed on the polysilicon plug structure contains little oxygen in the thin film, and has superior oxygen penetration prevention properties as compared to the CVD metal film, so that the lower portion of the capacitor is removed from the CVD metal film and the dielectric thin film thereon. The structure can reduce the diffusion of oxygen. On the other hand, oxygen present in the CVD metal film does not diffuse into the underlying structure but rather diffuses toward the dielectric thin film to serve as an oxygen source, thereby helping to maintain the oxygen stoichiometry of the dielectric thin film. In the present invention, the reason why the PVD metal film is mixed with CVD without using only the PVD metal film is that the PVD metal film cannot obtain sufficient step coverage in the capacitor having a three-dimensional structure such as an inner cylinder capacitor. It acts as a seed layer to make the step coverage of the CVD metal film even better.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 반도체 소자 제조 공정 중 캐패시터 형성 공정에 관한 것이며, 더 자세히는 금속 하부전극과 반도체 기판의 전기적인 콘택을 위해 폴리실리콘 플러그 구조를 사용한 반도체 소자의 캐패시터 형성방법을 가진 캐패시터 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a capacitor forming process in a semiconductor device manufacturing process. It relates to a method of forming an excitation capacitor.
반도체 메모리 소자의 고집적화에 따라 동일 레이아웃 면적에서 보다 큰 캐패시턴스를 확보하기 위한 노력이 계속되고 있다.As semiconductor memory devices become more integrated, efforts have been made to secure larger capacitances in the same layout area.
캐패시터의 캐패시턴스는 유전율(ε) 및 전극의 유효 표면적에 비례하고, 전극간 거리에 반비례하기 때문에, 종래에는 주로 캐패시터 하부전극의 표면적을 확보하거나 유전체의 박막화로 전극간 거리를 최소화하는 방향으로 많은 연구가 진행되어 왔다. 그러나, 이 중 유전체의 박막화는 누설전류 증가를 수반하는 문제점이 있으며, 이에 따라 캐패시터 구조를 플라나 스택(Planar stack), 콘케이브(Concave), 실린더(cylinder)와 같은 3차원 구조로 형성하여 캐패시터의 유효 표면적을 증대시키는 방법을 주로 사용하여 왔다.Since the capacitance of the capacitor is proportional to the dielectric constant (ε) and the effective surface area of the electrode, and is inversely proportional to the distance between electrodes, conventionally, many studies have been conducted mainly to secure the surface area of the capacitor lower electrode or to minimize the distance between electrodes by thinning the dielectric. Has been going on. However, thinning of the dielectric has a problem of increasing leakage current. Accordingly, the capacitor structure is formed into a three-dimensional structure such as a planar stack, a concave, and a cylinder to form a capacitor. The method of increasing the effective surface area has been mainly used.
그러나, 반도체 소자의 고집적화에 수반되는 디자인 룰의 축소에 따라 이러한 구조적인 개선을 통해 캐패시턴스를 확보하는 방법은 공정 상에 한계에 직면하게 되었다.However, with the reduction of design rules associated with high integration of semiconductor devices, the method of securing capacitance through such structural improvements has faced limitations in the process.
이에 따라, 현재는 기존의 유전체 재료인 NO(nitride/oxide) 박막을 Ta205, BST 등의 고유전체 박막이나 SBT,PZT, BLT와 같은 강유전체 박막으로 대체하는 방향으로 연구가 진행되고 있다.Accordingly, research is currently being conducted in the direction of replacing a conventional dielectric material NO (nitride / oxide) thin film with a high dielectric thin film such as Ta 2 O 5 , BST, or a ferroelectric thin film such as SBT, PZT, or BLT.
이와 같이 고유전체 박막이나 강유전체 박막을 사용하는 경우, 유전체 특성을 확보하기 위해서는 상/하부전극 및 주변 공정의 최적화가 이루어져야 하며, 이에 따라 상/하부전극 재료로 Ru, Pt, Ir, W 등의 금속막을 사용하고 있다.As described above, when using a high dielectric film or a ferroelectric thin film, top and bottom electrodes and peripheral processes should be optimized to secure dielectric properties. Accordingly, metals such as Ru, Pt, Ir, and W are used as top and bottom electrode materials. Membrane is used.
또한, 하부전극과 기판의 전기적 콘택을 위한 폴리실리콘 플러그와 금속 하부전극과의 오믹 콘택을 제공하고, 후속 열공정시 산소 확산에 따른 폴리실리콘 플러그 계면의 산화를 방지하기 위하여 TiN, Ti-Si-N, WN 등의 장벽금속층을 사용하고 있다. 고유전체 박막이나 강유전체 박막은 증착 및 결정화를 위해 고온의 산소 분위기를 필요로 하며, 캐패시터 구조 패터닝 후에는 플라즈마에 의한 유전체 박막의 열화를 회복시키기 위한 회복 열처리를 산소 분위기에서 실시하고 있다. 만일, 산소의 확산에 의해 폴리실리콘 플러그 계면에 얇은 산화막이 형성되면 2개의 캐패시터가 직렬로 연결된 구조가 이루어지기 때문에 캐패시턴스를 저하시키게 된다.In addition, in order to provide an ohmic contact between the polysilicon plug and the metal lower electrode for electrical contact between the lower electrode and the substrate, and to prevent oxidation of the polysilicon plug interface due to oxygen diffusion during the subsequent thermal process, TiN, Ti-Si-N , Barrier metal layers such as WN are used. High-k dielectric thin films and ferroelectric thin films require a high-temperature oxygen atmosphere for deposition and crystallization, and after the capacitor structure patterning, a recovery heat treatment is performed in the oxygen atmosphere to recover the degradation of the dielectric thin film by plasma. If a thin oxide film is formed on the polysilicon plug interface due to the diffusion of oxygen, the capacitance is reduced because the two capacitors are connected in series.
한편, 하부전극 재료인 Ru, Pt, Ir, W 등은 통상적으로 화학기상증착(CVD) 공정을 통해 형성하고 있는데, 이는 물리기상증착법으로 금속을 증착할 경우 스텝 커버리지가 열악하기 때문이다. 그런데, 이러한 CVD법을 통해 증착된 금속 박막 내에는 대부분 다량의 산소가 존재하게 되며, 이 산소가 후속 열공정시 유전체 박막 내의 산소와 함께 금속 박막 내에 존재하는 산소가 확산되어 장벽금속층 및 폴리실리콘 플러그의 산화를 유발하고, 유전체 박막의 산소 화학양론(oxygen stoichiometry) 불일치에 의한 캐패시턴스 손실 및 누설전류 특성 열화를 유발하고 있다.Meanwhile, the lower electrode materials Ru, Pt, Ir, W, and the like are typically formed through a chemical vapor deposition (CVD) process because the step coverage is poor when the metal is deposited by physical vapor deposition. However, a large amount of oxygen is present in the metal thin film deposited through the CVD method, and the oxygen is diffused in the metal thin film together with oxygen in the dielectric thin film during the subsequent thermal process, so that the barrier metal layer and the polysilicon plug Oxidation is caused, and capacitance loss and leakage current characteristics are deteriorated by oxygen stoichiometry mismatch of the dielectric thin film.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 특히 금속 하부전극 및 유전체 박막으로부터 캐패시터 하부 구조로 산소가 확산되는 것을 줄일 수 있는 반도체 소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and in particular, to provide a method for forming a capacitor of a semiconductor device that can reduce the diffusion of oxygen from the metal lower electrode and the dielectric thin film to the capacitor substructure. have.
도 1은 본 발명의 일 실시예에 따른 단순 스택형 고유전체 캐패시터 형성 공정도.1 is a process chart for forming a simple stack type high dielectric capacitor according to an embodiment of the present invention.
도 2는 본 발명의 다른 실시예에 따른 단순 스택형 고유전체 캐패시터 형성 공정도.2 is a process chart for forming a simple stacked high-k dielectric capacitor according to another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 실리콘 기판 11 : 층간절연막10 silicon substrate 11 interlayer insulating film
12 : 폴리실리콘 플러그 13 : 오믹콘택층 및 장벽금속층12 polysilicon plug 13 ohmic contact layer and barrier metal layer
14 : PVD Ru층 15 : CVD Ru층14: PVD Ru layer 15: CVD Ru layer
16 : BST막 17 : TiN막16: BST film 17: TiN film
상기의 기술적 과제를 달성하기 위하여 본 발명은, 하부전극과 반도체 기판의 전기적 콘택을 위해 폴리실리콘 플러그 구조를 사용한 반도체 소자의 캐패시터 형성방법에 있어서, 반도체 기판 상에 소정의 도전 구조 및 절연 구조를 구비한 하부층을 형성하는 제1 단계; 상기 하부층의 상기 절연 구조를 선택 식각하여 하부전극 콘택홀을 형성하는 제2 단계; 상기 하부전극 콘택홀 내에 폴리실리콘 플러그를 형성하는 제3 단계; 물리기상증착법을 사용하여 적어도 상기 폴리실리콘 플러그 상부에 제1 하부전극용 금속막을 적층시키는 제4 단계; 화학기상증착법을 사용하여 상기 제1 하부전극용 금속막 상에 제2 하부전극용 금속막을 적층시키는 제5 단계; 및 상기 제2 하부전극용 금속막 상에 유전체 박막 및 상부전극용 전도막을 적층시키는 제6 단계를 포함하여 이루어진다.In order to achieve the above technical problem, the present invention, in the method of forming a capacitor of a semiconductor device using a polysilicon plug structure for the electrical contact between the lower electrode and the semiconductor substrate, provided with a predetermined conductive structure and insulating structure on the semiconductor substrate Forming a lower layer; Selectively etching the insulating structure of the lower layer to form a lower electrode contact hole; Forming a polysilicon plug in the lower electrode contact hole; Stacking a metal film for the first lower electrode on at least the polysilicon plug by using physical vapor deposition; A fifth step of laminating a second lower electrode metal film on the first lower electrode metal film using a chemical vapor deposition method; And a sixth step of stacking a dielectric thin film and an upper electrode conductive film on the second lower electrode metal film.
바람직하게, 본 발명은 상기 제3 단계 수행 후, 상기 하부전극 콘택홀 내의 상기 폴리실리콘 플러그 상에 오믹콘택층 및 장벽금속층을 형성하는 제7 단계를 더 포함하여 이루어진다.Preferably, the present invention further includes a seventh step of forming an ohmic contact layer and a barrier metal layer on the polysilicon plug in the lower electrode contact hole after performing the third step.
바람직하게, 상기 제1 및 제2 하부전극용 금속막으로 각각 RU막, Ir막, Pt막, W막 중 어느 하나를 사용한다.Preferably, any one of an RU film, an Ir film, a Pt film, and a W film is used as the first and second lower electrode metal films.
바람직하게, 상기 장벽금속층으로 TiN/Ti막, Ti-Si-N막, WN막 중 어느 하나를 사용한다.Preferably, any one of a TiN / Ti film, a Ti-Si-N film, and a WN film is used as the barrier metal layer.
바람직하게, 상기 유전체 박막으로 Ta205막, BST막, PZT막, SBT막, BLT막 중 어느 하나를 사용한다.Preferably, any one of a Ta 2 O 5 film, a BST film, a PZT film, an SBT film, and a BLT film is used as the dielectric thin film.
바람직하게, 상기 상부전극용 전도막으로 TiN막, Ru막, W막 중 어느 하나를 사용한다.Preferably, any one of a TiN film, a Ru film, and a W film is used as the upper electrode conductive film.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 1은 본 발명의 일 실시예에 따른 단순 스택형 고유전체 캐패시터 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1 is a cross-sectional view illustrating a process of forming a simple stack type high dielectric capacitor according to an embodiment of the present invention.
우선, 실리콘 기판(10) 상에 소정의 절연 구조 및 도전 구조를 가지는 하부층(11)을 형성한다. 하부층(11)에는 워드라인, 비트라인 및 다수의 층간절연막이 포함되며, 하부전극 콘택 마스크를 사용한 사진 공정 및 층간절연막 식각 공정을 통해 하부전극 콘택홀을 형성한다.First, a lower layer 11 having a predetermined insulating structure and a conductive structure is formed on the silicon substrate 10. The lower layer 11 includes a word line, a bit line, and a plurality of interlayer insulating layers, and forms a lower electrode contact hole through a photo process using a lower electrode contact mask and an interlayer insulating layer etching process.
이어서, 하부전극 콘택홀 내에 폴리실리콘 플러그(12)를 형성한다. 이때, 폴리실리콘 플러그(12)가 콘택홀 상단으로부터 일정 깊이만큼 리세스 되어 형성되도록 하며, 이어서 콘택홀의 나머지 부분을 오믹콘택층 및 장벽금속층(13)으로 매립한다. 일반적으로, 오믹콘택을 위해 실리사이드막을 형성하며, 장벽금속으로는 TiN/Ti막, Ti-Si-N막, WN막 등을 사용한다.Next, a polysilicon plug 12 is formed in the lower electrode contact hole. At this time, the polysilicon plug 12 is recessed by a predetermined depth from the top of the contact hole, and then the remaining portion of the contact hole is filled with the ohmic contact layer and the barrier metal layer 13. In general, a silicide film is formed for ohmic contact, and as the barrier metal, a TiN / Ti film, a Ti-Si-N film, a WN film, or the like is used.
다음으로, PVD 공정을 통해 전체 구조 상부에 PVD Ru층(14)을 증착하고, CVD 공정을 통해 그 상부에 CVD Ru층(15)을 증착한다. 이때, PVD Ru층(14) 및 CVD Ru층(15)의 총 두께가 예정된 하부전극 두께에 해당하도록 한다. 한편, 하부전극 재료로 Ru 외에 Ir막, Pt막, W막 등을 사용할 수 있다.Next, the PVD Ru layer 14 is deposited on the entire structure through the PVD process, and the CVD Ru layer 15 is deposited on the upper portion thereof through the CVD process. At this time, the total thickness of the PVD Ru layer 14 and the CVD Ru layer 15 corresponds to the predetermined lower electrode thickness. As the lower electrode material, an Ir film, a Pt film, a W film, or the like can be used in addition to Ru.
계속하여, CVD Ru층(15) 상에 유전체 박막으로 BST막(16)을 증착하고, 결정화 열처리를 실시한 다음, 그 상부에 상부전극용 금속막으로 TiN막(17)을 증착한다. 이때, 유전체 박막으로 BST막(16) 외에 Ta205막, PZT막, SBT막, BLT막 등을 사용할 수 있으며, 상부전극용 전도막으로 TiN막(17) 외에 Ru막, W막 등을 사용할 수 있다.Subsequently, a BST film 16 is deposited on the CVD Ru layer 15 by a dielectric thin film, subjected to crystallization heat treatment, and then a TiN film 17 is deposited on the upper metal film for the upper electrode. At this time, the dielectric thin film in addition to BST film (16) Ta 2 0 5 film, PZT film, the SBT film, and the like BLT film, in addition to the Ru film top electrode TiN film 17 as a conductive membrane for, W film, etc. Can be used.
이후, 캐패시터 구조 패터닝 공정을 실시하고 회복 열처리를 실시한다.Subsequently, the capacitor structure patterning process is performed and a recovery heat treatment is performed.
한편, 첨부된 도면 도 2는 본 발명의 다른 실시예에 따른 단순 스택형 고유전체 캐패시터 형성 공정을 도시한 것으로, 상기 일 실시예의 공정에서 PVD Ru막(14)을 하부전극 콘택홀 영역에만 형성하는 것이다. 이때, PVD Ru막(14)은 도면에 도시된 바와 같이 콘택홀 내에 매립되는 구조로 형성할 수 있으며, 콘택홀 상부로 돌출되도록 형성 할 수 있다.Meanwhile, FIG. 2 is a diagram illustrating a simple stack type high dielectric capacitor forming process according to another embodiment of the present invention, in which the PVD Ru film 14 is formed only in the lower electrode contact hole region in the process of the above embodiment. will be. In this case, the PVD Ru film 14 may be formed to have a structure embedded in the contact hole as shown in the figure, it may be formed to protrude to the upper contact hole.
폴리실리콘 플러그 구조쪽에 배치된 PVD 금속막은 박막 내부에 산소를 거의 포함하지 않을 뿐만 아니라, CVD 금속막에 비해 산소 통과 방지 특성이 우수하기 때문에 CVD 금속막 및 그 상부의 유전체 박막으로부터 캐패시터 하부 구조로 산소가 확산되는 것을 줄일 수 있다. 한편, CVD 금속막 내에 존재하는 산소가 하부 구조로 확산되지 않고 오히려 유전체 박막 쪽으로 확산되어 산소 공급원으로 작용함으로써 유전체 박막의 산소 화학량론을 유지하는데 도움을 줄 수 있다. 본 발명에서 PVD 금속막만을 사용하지 않고 CVD와 혼용하는 이유는 이너 실린더 캐패시터와 같이 3차원 구조를 가지는 캐패시터에서 PVD 금속막만으로는 충분한 스텝 커버리지를 얻을 수 없기 때문이며, PVD 금속막이 후속 CVD 금속막 증착시 씨드(seed)층 역할을 수행하여 CVD 금속막의 스텝 커버리지를 더욱 좋게 만든다.The PVD metal film disposed on the polysilicon plug structure contains almost no oxygen in the thin film, and has superior oxygen passage prevention properties as compared to the CVD metal film, so that oxygen from the CVD metal film and its dielectric thin film to the capacitor substructure is increased. Can reduce the spread. On the other hand, oxygen present in the CVD metal film does not diffuse into the underlying structure but rather diffuses toward the dielectric thin film to serve as an oxygen source, thereby helping to maintain the oxygen stoichiometry of the dielectric thin film. In the present invention, the reason why the PVD metal film is not mixed with the CVD without using only the PVD metal film is that the PVD metal film cannot obtain sufficient step coverage in the capacitor having a three-dimensional structure such as an inner cylinder capacitor. It acts as a seed layer to make the step coverage of the CVD metal film even better.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속한 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 단순 스택형 캐패시터를 일례로 들어 설명하였으나, 본 발명은 플라나 스택, 콘케이브, 실린더 등의 3차원 구조의 캐패시터를 형성하는 공정에도 적용할 수 있다.For example, in the above-described embodiment, a simple stacked capacitor has been described as an example, but the present invention can be applied to a process of forming a capacitor having a three-dimensional structure such as a planar stack, a concave, a cylinder, and the like.
전술한 본 발명은 하부전극 및 유전체 박막으로부터 캐패시터 하부 구조 즉, 폴리실리콘 플러그 및 장벽금속층으로 산소가 확산되는 것을 크게 줄일 수 있으며, 이로 인하여 안정된 캐패시턴스를 확보할 수 있는 효과가 있다. 또한, 본 발명은 하부전극용 금속막의 스텝 커버리지를 개선하는 효과를 기대할 수 있다.The present invention described above can greatly reduce the diffusion of oxygen from the lower electrode and the dielectric thin film to the capacitor substructure, that is, the polysilicon plug and the barrier metal layer, thereby ensuring a stable capacitance. In addition, the present invention can be expected to improve the step coverage of the metal film for the lower electrode.
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| JPH11145423A (en) * | 1997-11-13 | 1999-05-28 | Nec Corp | Manufacture of semiconductor device |
| KR20010093456A (en) * | 2000-03-29 | 2001-10-29 | 박종섭 | Method of forming interconnections in semiconductor devices |
| KR20010108994A (en) * | 2000-06-01 | 2001-12-08 | 박종섭 | Method for manu facturing capa citor in semiconductor memory divice |
| KR100418580B1 (en) * | 2001-06-12 | 2004-02-21 | 주식회사 하이닉스반도체 | Method of forming a capacitor of a semiconductor device |
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| JPH11145423A (en) * | 1997-11-13 | 1999-05-28 | Nec Corp | Manufacture of semiconductor device |
| KR20010093456A (en) * | 2000-03-29 | 2001-10-29 | 박종섭 | Method of forming interconnections in semiconductor devices |
| KR20010108994A (en) * | 2000-06-01 | 2001-12-08 | 박종섭 | Method for manu facturing capa citor in semiconductor memory divice |
| KR100418580B1 (en) * | 2001-06-12 | 2004-02-21 | 주식회사 하이닉스반도체 | Method of forming a capacitor of a semiconductor device |
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