KR100275113B1 - A method for fabricating ferroelectric capacitor in semiconductor device - Google Patents

A method for fabricating ferroelectric capacitor in semiconductor device Download PDF

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KR100275113B1
KR100275113B1 KR1019970078021A KR19970078021A KR100275113B1 KR 100275113 B1 KR100275113 B1 KR 100275113B1 KR 1019970078021 A KR1019970078021 A KR 1019970078021A KR 19970078021 A KR19970078021 A KR 19970078021A KR 100275113 B1 KR100275113 B1 KR 100275113B1
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film
titanium
titanium nitride
nitride film
lower electrode
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KR19990057942A (en
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이창구
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

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Abstract

PURPOSE: A fabrication method of a ferroelectric capacitor is provided to improve properties of capacitors by easily achieving a thermal stability of a lower electrode. CONSTITUTION: After forming an interlayer dielectric(16) on a semiconductor substrate(10), a contact hole is formed by patterning the interlayer dielectric. A polysilicon plug(17) is filled into the contact hole. A titanium-rich TiN film(18) is deposited on the resultant structure. A titanium silicide film(19) is formed at interface between the titanium-rich TiN film(18) and the polysilicon plug(17) and a dense TiON film is formed on the surface of the titanium-rich TiN film(18) by annealing. A nitrogen-rich TiN film(20) is deposited on the resultant structure. The nitrogen-rich TiN film(20) includes oxygen. Then, a lower electrode is formed on the nitrogen-rich TiN film(20).

Description

반도체 장치의 강유전체 캐패시터 제조방법{A method for fabricating ferroelectric capacitor in semiconductor device}A method for fabricating ferroelectric capacitor in semiconductor device

본 발명은 반도체 제조 분야에 관한 것으로, 특히 강유전체 메모리 소자(FeRAM) 및 차세대 초고집적 DRAM에 적용되는 반도체 장치의 강유전체 캐패시터 제조 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a ferroelectric capacitor manufacturing process of a semiconductor device applied to a ferroelectric memory device (FeRAM) and a next generation ultra high density DRAM.

종래에는 반도체 장치의 동작 특성 확보에 충분한 정전용량을 제공하기 위하여 캐패시터의 하부전극을 3차원 구조화하거나, 유전체 두께를 감소시키는 방법을 사용하여 왔다. 그러나, 이러한 방법은 반도체 장치의 고집적화에 따라 그 적용 한계에 직면하게 되었다.Conventionally, in order to provide a capacitance sufficient to secure operating characteristics of a semiconductor device, a method of three-dimensional structuring a lower electrode of a capacitor or reducing a dielectric thickness has been used. However, this method has faced its application limitations due to the high integration of semiconductor devices.

이에 따라, FeRAM 및 향후 차세대 반도체 메모리 장치의 캐패시터의 유전막으로서 SrBi2Ti2O3(이하, SBT라 함), Pb(Zr,Ti)O3(이하, PZT라 함) 등의 고유전체 물질을 사용하는 고유전체 캐패시터에 대한 연구·개발이 진행되고 있다.Accordingly, high dielectric materials such as SrBi 2 Ti 2 O 3 (hereinafter referred to as SBT) and Pb (Zr, Ti) O 3 (hereinafter referred to as PZT) are used as dielectric films for FeRAM and capacitors of future generations of semiconductor memory devices. Research and development of high-k dielectric capacitors in use is underway.

이러한 고유전체 캐패시터의 하부전극 재료로서 백금(Pt)이 유력시되고 있으며, 통상적으로 백금 하부전극과 기판간의 불순물 상호 확산을 방지하기 위한 확산방지막을 사용하는데, 확산방지막으로는 티타늄/질화티타늄막(Ti/TiN막)이 주로 사용되고 있다.As a lower electrode material of such a high-k dielectric capacitor, platinum (Pt) is a strong material, and a diffusion barrier layer for preventing the diffusion of impurities between the platinum lower electrode and the substrate is generally used. As a diffusion barrier layer, a titanium / titanium nitride film (Ti) is used. / TiN film) is mainly used.

통상적으로 폴리실리콘 플러그와 하부전극 사이에 오믹 콘택을 제공하기 위하여 실리사이드를 형성하고 있다. 즉, 고온의 고유전체 박막 증착 공정 및 층간절연막으로 사용되는 BPSG막 증착 공정과 같은 850℃ 이상의 후속 열처리 공정에 의해 티타늄막이 하부의 실리콘 기판 또는 폴리실리콘 플러그 내의 실리콘(Si)과 반응하여 티타늄실리사이드막을 형성하는데, 이때 티타늄실리사이드막의 응집 현상이 발생하여 상부의 질화티타늄막을 깨뜨리는 문제점이 있었다.Typically, silicide is formed to provide an ohmic contact between the polysilicon plug and the lower electrode. That is, the titanium film is reacted with silicon (Si) in the lower silicon substrate or the polysilicon plug by a subsequent heat treatment process of 850 ° C. or higher, such as a high temperature high dielectric film deposition process and a BPSG film deposition process used as an interlayer insulating film. In this case, there is a problem in that the agglomeration phenomenon of the titanium silicide film occurs to break the upper titanium nitride film.

또한, 하부전극인 백금막 증착 후 열처리 과정을 통한 산소 확산으로 질화티타늄막 표면에 큰 인장 응력을 유발하는 티타늄산화막(TiO2)이 형성되어 백금막 표면에 버블(bubble) 형태의 결함 발생을 유발하는 문제점이 있다. 즉, 하부전극의 열적 안정성이 매우 열악해지는 문제점이 있었다.In addition, a titanium oxide film (TiO 2 ) is formed on the surface of the titanium nitride film to induce a large tensile stress by the diffusion of oxygen through the heat treatment process after deposition of the platinum film, which is a lower electrode, causing a bubble-shaped defect on the surface of the platinum film. There is a problem. That is, there is a problem that the thermal stability of the lower electrode is very poor.

본 발명은 반도체 장치의 강유전체 캐패시터 제조 공정시 하부전극의 열적 안정성을 확보할 수 있는 강유전체 캐패시터의 하부전극 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a lower electrode of a ferroelectric capacitor capable of securing thermal stability of a lower electrode in a ferroelectric capacitor manufacturing process of a semiconductor device.

도 1a 내지 도 1f는 본 발명의 일 실시예에 따른 반도체 장치의 강유전체 캐패시터 및 그 제조 공정도.1A to 1F are ferroelectric capacitors and a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 실리콘 기판 11 : 소자 분리막10 silicon substrate 11 device isolation film

12 : 게이트 산화막 13 : 워드라인12 gate oxide film 13 word line

14 : 스페이서 산화막 15 : 접합 영역14 spacer oxide film 15 junction region

16 : 층간절연막 17 : 폴리실리콘 플러그16: interlayer insulating film 17: polysilicon plug

18 : 제1 질화티타늄막 19 : 티타늄실리사이드막18: first titanium nitride film 19: titanium silicide film

20 : 제2 질화티타늄막 21, 25 : 백금막20: second titanium nitride film 21, 25: platinum film

22 : PZT막 23 : TiO2막22: PZT film 23: TiO 2 film

24 : 실리콘질화막 26 : BPSG막24 silicon nitride film 26 BPSG film

상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 강유전체 캐패시터의 하부전극 형성방법은, 반도체 기판 상에 형성된 층간절연막에 콘택홀을 형성하고 상기 콘택홀 내에 실리콘 플러그를 형성하는 제1 단계; 상기 제1 단계를 마친 전체구조 상부에 제1 질화티타늄막을 증착하되, 상기 제1 질화티타늄막 내에 잉여 티타늄이 존재하도록 하는 제2 단계; 산화 분위기에서 열처리를 실시하여 상기 제1 질화티타늄막과 상기 실리콘 플러그의 계면에 티타늄실리사이드막을 형성하고 상기 제1 질화티타늄막 표면에 산화질화티타늄막을 형성하는 제3 단계; 상기 제1 질화티타늄막 상부에 제2 질화티타늄막을 증착하되, 상기 제2 질화티타늄막 내에 잉여 질소가 존재하도록 하며, 산소를 포함하여 산화질화티타늄막의 형태를 가지도록 하는 제4 단계; 및 상기 제2 질화티타늄막 상부에 하부전극용 전도막을 형성하는 제5 단계를 포함하여 이루어진다.According to another aspect of the present invention, there is provided a method of forming a lower electrode of a ferroelectric capacitor, the method including: forming a contact hole in an interlayer insulating layer formed on a semiconductor substrate and forming a silicon plug in the contact hole; A second step of depositing a first titanium nitride film on the entire structure after the first step, wherein excess titanium is present in the first titanium nitride film; Performing a heat treatment in an oxidizing atmosphere to form a titanium silicide film at an interface between the first titanium nitride film and the silicon plug and to form a titanium oxide nitride film on the surface of the first titanium nitride film; Depositing a second titanium nitride film on the first titanium nitride film, allowing excess nitrogen to exist in the second titanium nitride film, and including oxygen to have a form of a titanium oxynitride film; And a fifth step of forming a conductive film for the lower electrode on the second titanium nitride film.

즉, 본 발명에서는 하부전극 확산방지막으로 사용되는 질화티타늄막을 증착시 질소 함유량을 달리하여 2 단계로 증착한다. 먼저, 제1 질화티타늄막의 증착은 질소 함량이 적은 분위기에서 증착하여 질화티타늄 내에 티타늄 성분의 함량이 상대적으로 많도록 하고, 바로 산소 분위기의 튜브에서 열처리하여 미리 티타늄실리사이드막을 형성함으로써 후속 열처리 과정에서의 질화티타늄막의 깨어짐을 방지한다. 또한, 산소 분위기에서의 열처리에 의해 질화티타늄 표면을 조밀한 산화질화티타늄(TiON)막으로 만들어서 하부 실리콘으로부터 더 이상의 확산을 막아 준다. 제2 질화티타늄막은 막 내의 질소 함유량이 상대적으로 많도록 하여 성긴 막 구조를 형성함으로써 미리 막 내에 산소를 다량 함유시켜 TiON의 막 구조로 바꿔줌으로써 후속 열처리 과정에서의 산소 확산에 의한 티타늄산화막의 형성을 억제한다. 즉, 본 발명은 확산방지막인 질화티타늄막의 2 단계 증착을 통해 하부전극의 열적 안정성을 향상시키는 기술이다.That is, in the present invention, the titanium nitride film used as the lower electrode diffusion barrier film is deposited in two steps by varying the nitrogen content. First, the deposition of the first titanium nitride film is carried out in an atmosphere of low nitrogen content so that the titanium component is relatively high in titanium nitride, and immediately heat-treated in an oxygen atmosphere tube to form a titanium silicide film in the subsequent heat treatment process. Prevents the titanium nitride film from cracking. In addition, the heat treatment in an oxygen atmosphere makes the titanium nitride surface a dense titanium oxynitride (TiON) film to prevent further diffusion from the underlying silicon. The second titanium nitride film has a relatively high content of nitrogen in the film to form a coarse film structure, thereby containing a large amount of oxygen in the film beforehand and converting it into a film structure of TiON, thereby forming a titanium oxide film by oxygen diffusion in a subsequent heat treatment process. Suppress That is, the present invention is a technique for improving the thermal stability of the lower electrode through the two-step deposition of the titanium nitride film as a diffusion barrier.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 1a 내지 도 1f는 본 발명의 일 실시예에 따른 강유전체 캐패시터 제조 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.1A to 1F illustrate a ferroelectric capacitor manufacturing process according to an exemplary embodiment of the present invention. Hereinafter, the process will be described with reference to the accompanying drawings.

우선, 도 1a에 도시된 바와 같이 소자 분리막(11) 및 트랜지스터 형성 공정을 마친 실리콘 기판(10) 상부에 층간절연막(16)을 증착하고, 이를 선택 식각하여 접합 영역(15)을 노출시키는 콘택홀을 형성한 다음, 화학기상증착법으로 전체구조 상부에 폴리실리콘막을 증착하고, 이를 에치백하여 폴리실리콘 플러그(17)를 형성한다. 도면 부호 '12'는 게이트 산화막, '13'은 워드라인, '14'는 스페이서 산화막을 각각 나타낸 것이다.First, as shown in FIG. 1A, an interlayer insulating layer 16 is deposited on the silicon isolation layer 10 after the process of forming the device isolation layer 11 and the transistor, and then selectively etched to expose the junction region 15. After forming a, a polysilicon film is deposited on the entire structure by chemical vapor deposition, and etched back to form a polysilicon plug (17). Reference numeral '12' denotes a gate oxide layer, '13' a word line, and '14' denotes a spacer oxide layer.

다음으로, 도 1b에 도시된 바와 같이 전체구조 상부에 제1 질화티타늄막(18)을 증착하고, 산소 분위기 및 500℃ 이상의 온도에서 열처리를 실시하여 제1 질화티타늄막(18)의 표면에 막 구조가 조밀한 TiON막을 형성하고, 제1 질화티타늄막(18) 내의 티타늄(Ti)과 폴리실리콘 플러그(17)의 실리콘(Si)을 반응시켜 그 계면 부분에서 티타늄실리사이드막(19)을 형성한다. 단, 제1 질화티타늄막(18) 증착시에는 질소 함유량이 적은 상태에서 스퍼터링 증착하여 제1 질화티타늄막(18) 내에 티타늄(Ti)의 함량이 상대적으로 많게 한다. 이는 후속 실리사이드 반응을 고려한 것이다.Next, as illustrated in FIG. 1B, a first titanium nitride film 18 is deposited on the entire structure, and heat treated at an oxygen atmosphere and at a temperature of 500 ° C. or higher to form a film on the surface of the first titanium nitride film 18. A dense TiON film is formed, and titanium (Ti) in the first titanium nitride film 18 is reacted with silicon (Si) of the polysilicon plug 17 to form a titanium silicide film 19 at the interface portion thereof. . However, when the first titanium nitride film 18 is deposited, sputtering deposition is performed in a state where the nitrogen content is low so that the content of titanium (Ti) is relatively high in the first titanium nitride film 18. This takes into account subsequent silicide reactions.

계속하여, 도 1c에 도시된 바와 같이 스퍼터링 챔버 내의 질소량을 많게 하고 증착 온도가 상온인 상태에서 막 내에 잉여 질소 함유량이 많은 제2 질화티타늄막(20)을 제1 질화티타늄막(18) 상에 증착한다. 이때, 제2 질화티타늄막(20)은 잉여 질소에 의해 성긴 막 구조를 가지기 때문에 막 내에 산소가 많이 함유된 TiON 구조를 쉽게 형성할 수 있다. 즉, 제2 질화티타늄막(20)은 다량의 산소가 함유된 TiON막이 된다. 이러한 제2 질화티타늄막(20)은 후속 강유전체 박막 열처리 과정에서 산소 확산으로 인한 티타늄산화막(TiO2)의 형성을 억제하는 역할을 수행한다. 위에서, 제1 및 제2 질화티타늄막(18, 20)의 전체 두께는 200∼2000Å로 증착하되, 각각 거의 같은 두께로 증착할 수 있다.Subsequently, as shown in FIG. 1C, the second titanium nitride film 20 having a large amount of excess nitrogen in the film is formed on the first titanium nitride film 18 while the amount of nitrogen in the sputtering chamber is increased and the deposition temperature is room temperature. Deposit. At this time, since the second titanium nitride film 20 has a sparse film structure by excess nitrogen, it is possible to easily form a TiON structure containing much oxygen in the film. That is, the second titanium nitride film 20 becomes a TiON film containing a large amount of oxygen. The second titanium nitride film 20 serves to suppress the formation of the titanium oxide film TiO 2 due to oxygen diffusion in the subsequent ferroelectric thin film heat treatment process. In the above, the total thicknesses of the first and second titanium nitride films 18 and 20 are deposited at 200 to 2000 microseconds, but they can be deposited at almost the same thickness.

이어서, 도 1d에 도시된 바와 같이 전체구조 상부에 하부전극으로서 1000∼3000Å 두께의 백금막(21) 및 PZT막(22)을 형성하고, PZT막(22) 및 백금막(21)을 차례로 선택 식각하여 스토리지 노드를 디파인한다.Subsequently, as shown in FIG. 1D, a platinum film 21 and a PZT film 22 having a thickness of 1000 to 3000 Å are formed as a lower electrode on the entire structure, and the PZT film 22 and the platinum film 21 are sequentially selected. Detach the storage nodes by etching.

다음으로, 도 1e에 도시된 바와 같이 캐패시터 보호막(capacitor barrier)인 TiO2막(23) 및 실리콘산화막(SiO2)(24)을 전체구조 상부에 차례로 증착한 다음, 이를 패터닝하여 실제 캐패시터의 면적을 정의한다.Next, as shown in FIG. 1E, a TiO 2 film 23 and a silicon oxide film (SiO 2 ) 24, which are capacitor barriers, are sequentially deposited on the entire structure, and then patterned. The area of the actual capacitor is then deposited. Define.

끝으로, 도 1f에 도시된 바와 같이 전체구조 상부에 백금막(25)을 증착하고 이를 패터닝하여 상부전극을 정의하고, 전체구조 상부에 층간절연막인 BPSG막(26)을 증착하여 절연을 이룬다.Finally, as illustrated in FIG. 1F, the platinum film 25 is deposited on the entire structure and patterned to define the upper electrode, and the BPSG film 26, which is an interlayer insulating film, is deposited on the entire structure to form insulation.

상기와 같은 공정을 통해 강유전체 캐패시터를 형성하면 즉, 폴리실리콘 플러그와 접촉하는 확산방지막으로 질화티타늄막을 증착하되 박막 내에 잉여 티타늄이 존재하도록 하여 이어지는 실리사이드화 열처리에서 잉여 티타늄이 공급되도록 하고, 또한 후속 열공정이 아닌 실리사이드 결정화 온도에 가까운 고온의 산소 분위기에서 실리사이드 열처리를 실시함으로써 실리사이드의 응집 현상을 최소화하였다.When the ferroelectric capacitor is formed through the above process, that is, the titanium nitride film is deposited by the diffusion barrier film in contact with the polysilicon plug, and the excess titanium is present in the thin film so that the surplus titanium is supplied in the subsequent silicided heat treatment, and further subsequent breakdown The silicide agglomeration phenomenon was minimized by performing a silicide heat treatment in a high temperature oxygen atmosphere close to the silicide crystallization temperature rather than the crystal.

또한, 하부전극과 접촉하는 확산방지막으로 질화티타늄을 증착하되 박막 내에 잉여 질소가 잔류하는데, 이는 보다 성긴 막 구조를 가지도록 하여 막 내에 산소가 많이 함유된 TiON 구조로 형성하고, 후속 열공정시 하부전극을 통한 산소의 확산으로 인한 티타늄산화막(TiO2)의 형성을 억제하는 효과를 극대화하기 위함이다.Further, titanium nitride is deposited as a diffusion barrier in contact with the lower electrode, and excess nitrogen remains in the thin film, which has a more coarse film structure, thereby forming a TiON structure containing oxygen in the film, and the lower electrode in a subsequent thermal process. This is to maximize the effect of inhibiting the formation of titanium oxide (TiO 2 ) due to the diffusion of oxygen through.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

예컨대, 전술한 일 실시예에서는 상부전극 및 하부전극으로 각각 백금막으로 사용하는 경우를 일례로 들어 설명하였으나, 이는 본 발명의 바람직한 실시예를 밝힌 것으로, 본 발명은 캐패시터의 상/하부전극 재료로 다른 전도막 사용하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, the case of using the platinum film as the upper electrode and the lower electrode, respectively, has been described as an example. However, the present invention discloses a preferred embodiment of the present invention. The same applies to the case of using other conductive films.

또한, 본 발명은 유전체 박막으로 PZT막 외의 다른 강유전체 물질을 사용하는 경우에도 적용할 수 있다.In addition, the present invention can be applied to the case of using a ferroelectric material other than the PZT film as the dielectric thin film.

이상에서와 같이 본 발명은 하부전극의 열적 안정성을 확보하여 캐패시터의 특성을 개선하는 효과가 있으며, 이로 인하여 차세대 고집적 DRAM 및 강유전체 메모리 소자의 신뢰도 및 성능의 향상을 기대할 수 있다.As described above, the present invention has the effect of securing the thermal stability of the lower electrode to improve the characteristics of the capacitor, thereby improving the reliability and performance of the next generation of highly integrated DRAM and ferroelectric memory devices.

Claims (2)

반도체 기판 상에 형성된 층간절연막에 콘택홀을 형성하고 상기 콘택홀 내에 실리콘 플러그를 형성하는 제1 단계;Forming a contact hole in the interlayer insulating film formed on the semiconductor substrate and forming a silicon plug in the contact hole; 상기 제1 단계를 마친 전체구조 상부에 제1 질화티타늄막을 증착하되, 상기 제1 질화티타늄막 내에 잉여 티타늄이 존재하도록 하는 제2 단계;A second step of depositing a first titanium nitride film on the entire structure after the first step, wherein excess titanium is present in the first titanium nitride film; 산화 분위기에서 열처리를 실시하여 상기 제1 질화티타늄막과 상기 실리콘 플러그의 계면에 티타늄실리사이드막을 형성하고 상기 제1 질화티타늄막 표면에 산화질화티타늄막을 형성하는 제3 단계;Performing a heat treatment in an oxidizing atmosphere to form a titanium silicide film at an interface between the first titanium nitride film and the silicon plug and to form a titanium oxide nitride film on the surface of the first titanium nitride film; 상기 제1 질화티타늄막 상부에 제2 질화티타늄막을 증착하되, 상기 제2 질화티타늄막 내에 잉여 질소가 존재하도록 하며, 산소를 포함하여 산화질화티타늄막의 형태를 가지도록 하는 제4 단계; 및Depositing a second titanium nitride film on the first titanium nitride film, allowing excess nitrogen to exist in the second titanium nitride film, and including oxygen to have a form of a titanium oxynitride film; And 상기 제2 질화티타늄막 상부에 하부전극용 전도막을 형성하는 제5 단계A fifth step of forming a conductive film for the lower electrode on the second titanium nitride film 를 포함하여 이루어진 강유전체 캐패시터의 하부전극 형성방법.A method of forming the lower electrode of the ferroelectric capacitor comprising a. 제1항에 있어서,The method of claim 1, 상기 제1 및 제2 질화티타늄막의 두께의 합이 200 내지 2000Å인 것을 특징으로 하는 강유전체 캐패시터의 하부전극 형성방법.And a sum of the thicknesses of the first and second titanium nitride films is 200 to 2000 mW.
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