KR100454758B1 - Method of depositing tantalum oxide layer - Google Patents
Method of depositing tantalum oxide layer Download PDFInfo
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- KR100454758B1 KR100454758B1 KR10-2002-0002109A KR20020002109A KR100454758B1 KR 100454758 B1 KR100454758 B1 KR 100454758B1 KR 20020002109 A KR20020002109 A KR 20020002109A KR 100454758 B1 KR100454758 B1 KR 100454758B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
Abstract
가성 원자층 증착법(Pseudo Atomic Layer Deposition)을 이용한 탄탈륨 산화막 증착방법에 관해 개시하고 있다. 본 발명은, 탄탈륨 산화막 증착초기에 가성 원자층 증착법을 적용하고 그 이후에 화학기상 증착법을 적용하여 원하는 두께의 탄탈륨 산화막을 증착시키는 것을 특징으로 한다. 본 발명에 따르면, 탄탈륨 산화막과 그 하부구조의 계면에서 탄소, 수소 등의 불순물을 현저히 줄일 수 있을 뿐 아니라 단차피복성이 우수한 탄탈륨 산화막을 얻을 수 있다.A method of depositing a tantalum oxide film using a pseudo atomic layer deposition method is disclosed. The present invention is characterized by depositing a tantalum oxide film having a desired thickness by applying a caustic atomic layer deposition method at the beginning of tantalum oxide film deposition and then applying a chemical vapor deposition method. According to the present invention, it is possible to significantly reduce impurities such as carbon and hydrogen at the interface between the tantalum oxide film and its substructure, and to obtain a tantalum oxide film having excellent step coverage.
Description
본 발명은 탄탈륨 산화막 증착방법에 관한 것으로, 특히 가성 원자층 증착법(Pseudo Atomic Layer Deposition)을 이용한 탄탈륨 산화막 증착방법에 관한 것이다.The present invention relates to a tantalum oxide film deposition method, and more particularly to a tantalum oxide film deposition method using pseudo atomic layer deposition (Pseudo Atomic Layer Deposition).
요즘, 반도체 소자의 집적도가 높아짐에 따라 셀의 면적이 급격하게 축소되는 추세에 있다. 셀의 면적이 축소되면 셀의 정전용량이 줄어드는데, 반도체 소자가 우수한 특성을 가지기 위해서는 셀 면적의 축소에도 불구하고 셀 정전용량이 일정용량 이상으로 유지되어야 한다. 따라서, 셀 동작에 필요한 정전용량은 그대로 유지하면서 반도체 소자의 신뢰성도 확보할 수 있는 공정개발이 필요한 상황이다.Nowadays, as the integration degree of semiconductor devices increases, the area of cells is rapidly decreasing. When the area of the cell is reduced, the cell capacitance is reduced. In order for the semiconductor device to have excellent characteristics, the cell capacitance must be maintained above a certain capacity despite the reduction in the cell area. Therefore, there is a need for a process development that can ensure the reliability of semiconductor devices while maintaining the capacitance required for cell operation.
종래에는 실리콘질화막 및 실리콘산화막의 복합층을 유전막으로 이용하는 NO(Nitride-Oxide) 캐퍼시터가 많이 사용되었다. 그런데, 이 NO 캐퍼시터는, 캐퍼시터용 전극의 표면적을 증가시키기 위해 반구형실리콘(HemiSpherical Grain)을 이용한다 할지라도, 현재 반도체 소자에서 요구되는 고유전률을 충족시키지 못하는 실정이다. 그 이유는 실리콘질화막과 실리콘산화막의 유전률이 각각 7과 3.5로서낮은 값을 갖기 때문이다.Conventionally, NO (Nitride-Oxide) capacitors using a composite layer of a silicon nitride film and a silicon oxide film as a dielectric film have been used. By the way, this NO capacitor does not meet the high dielectric constant currently required by a semiconductor device, even if hemispherical silicon (HemiSpherical Grain) is used to increase the surface area of the capacitor electrode. The reason is that the dielectric constants of the silicon nitride film and the silicon oxide film have low values as 7 and 3.5, respectively.
그래서 최근에, 실리콘질화막 및 실리콘산화막의 복합층이 가지는 저유전률의 단점을 보완하기 위해, 고유전막 재료로서 탄탈륨 산화막(Ta2O5)을 사용하고 있다. 이 탄탈륨 산화막은 유전률이 25 정도로서 비교적 높은 값을 갖는다.In recent years, a tantalum oxide film (Ta 2 O 5 ) has been used as a high dielectric film material in order to compensate for the disadvantage of the low dielectric constant of the composite layer of the silicon nitride film and the silicon oxide film. This tantalum oxide film has a relatively high dielectric constant of about 25.
한편, 이와 같은 탄탈륨 산화막을 형성시키는 경우에, 전구체로서 탄탈륨 펜타 에톡사이드{PET:Ta(OC2H5)5}라는 유기화합물이 널리 사용되고 있으며 이러한 전구체는 상온에서 액체 상태로 유지되어 있으므로 화학기상 증착공정에 의하여 탄탈륨 산화막을 증착시키기 위하여 기화기(vaporizer)에서 기화시킨 후 가스 라인을 통하여 반응기로 유입시킨다. 반응기 내에는 반도체 기판이 장착되어 공정 온도로 가열된 후, 가스 유량, 압력 등의 공정 조건이 안정화되는 시간을 거친 후에 반응가스인 산소와 PET를 반응기에 주입하여 탄탈륨 산화막을 반도체 기판 상에 증착하게 된다.On the other hand, in the formation of such a tantalum oxide film, an organic compound called tantalum penta ethoxide {PET: Ta (OC 2 H 5 ) 5 } is widely used as a precursor, and since the precursor is maintained in a liquid state at room temperature, chemical In order to deposit the tantalum oxide film by the deposition process, the vaporizer is vaporized in a vaporizer and then introduced into the reactor through a gas line. After the semiconductor substrate is mounted in the reactor and heated to the process temperature, the process gas such as gas flow rate and pressure is stabilized, and then oxygen and PET, which are reactive gases, are injected into the reactor to deposit a tantalum oxide film on the semiconductor substrate. do.
그러나, PET 소스는 분자식으로부터 알 수 있듯이 많은 양의 탄소와 수소를 함유하고 있으므로 증착된 탄탈륨 산화막과 그 하부구조의 계면에 다량의 탄소와 수소 불순물이 포함되어 계면특성을 악화시킴으로써 결과적으로 반도체 메모리 장치의 성능 및 신뢰도를 저하시키는 문제점이 야기된다.However, since PET source contains a large amount of carbon and hydrogen, as can be seen from the molecular formula, a large amount of carbon and hydrogen impurities are included at the interface between the deposited tantalum oxide film and its substructure, resulting in deterioration of the interface characteristics. The problem of lowering the performance and reliability of is caused.
한편, 상기한 계면 특성의 문제를 개선하기 위해 탄탈륨 산화막의 형성 후에 열처리를 거치기도 하지만 이는 열 버짓(thermal budget)에 대한 또 다른 문제를 발생시킬 수 있다.On the other hand, the heat treatment after the formation of the tantalum oxide film to improve the problem of the interfacial properties, but may cause another problem for the thermal budget (thermal budget).
한편, 박막을 이루는 성분 원소의 원료를 동시에 공급하는 통상의 화학기상 증착방법과는 달리 원료를 순차적으로 공급하여 기판 표면의 화학 반응에 의해서만 박막을 형성하는 원자층 증착법을 전체적으로 적용하여 상기한 계면특성의 문제를 해결할 수도 있으나 원자층 증착법에 의하면 막의 증착속도가 늦어서 쓰루-풋(throughput)의 문제가 발생할 수 있다.On the other hand, unlike the conventional chemical vapor deposition method of simultaneously supplying the raw materials of the constituent elements constituting the thin film, the above-described interface characteristics are applied by applying the atomic layer deposition method of supplying the raw materials sequentially to form a thin film only by chemical reaction on the surface of the substrate. Although the problem may be solved, the atomic layer deposition method may cause a problem of through-put due to the slow deposition rate of the film.
따라서, 본 발명의 기술적 과제는, PET 소스를 이용하여 탄탈륨 산화막을 증착시킴에 있어서, 탄탈륨 산화막과 그 하부구조의 계면에 통상적으로 생성되는 탄소와 수소 불순물의 생성을 저감시킬 수 있는 탄탈륨 산화막 증착방법을 제공하는 것이다.Accordingly, a technical problem of the present invention is that in depositing a tantalum oxide film using a PET source, a tantalum oxide film deposition method capable of reducing the generation of carbon and hydrogen impurities typically generated at the interface between the tantalum oxide film and its substructure. To provide.
상기한 기술적 과제를 해결하기 위한 본 발명의 탄탈륨 산화막 증착방법은:Tantalum oxide film deposition method of the present invention for solving the above technical problem is:
(a) 화학기상 증착 반응기 내에 반도체 기판을 위치시키는 단계와;(a) positioning the semiconductor substrate in a chemical vapor deposition reactor;
(b) 상기 기판을 공정 온도까지 가열하는 단계와;(b) heating the substrate to a process temperature;
(c) 압력 조절 없이 기본 진공압을 유지한 상태에서 탄탈륨 소스가스인 PET를 상기 반응기 내에 도입하는 단계와;(c) introducing PET, a tantalum source gas, into the reactor while maintaining a basic vacuum without pressure adjustment;
(d) 상기 반응기 내부를 퍼지하기 위한 아르곤 가스를 반응기 내에 도입하는 단계와;(d) introducing an argon gas into the reactor to purge the interior of the reactor;
(e) 반응가스인 산소를 상기 반응기 내에 도입하는 단계와;(e) introducing oxygen as a reaction gas into the reactor;
(f) 상기 반응기 내부를 퍼지하기 위한 아르곤 가스를 반응기 내에 도입하는 단계와;(f) introducing an argon gas into the reactor to purge the interior of the reactor;
(g) 상기 (c) 단계 내지 (f) 단계를 2∼3회 반복하는 단계와;(g) repeating steps (c) to (f) two to three times;
(h) 상기 반응기 내를 공정 압력이 되도록 감압시키는 단계와;(h) depressurizing the reactor to a process pressure;
(i) 상기 반응기 내에 탄탈륨 소스가스인 PET와 반응가스인 산소를 동시에 도입하는 단계;(i) simultaneously introducing PET, a tantalum source gas, and oxygen, a reaction gas, into the reactor;
를 구비하는 것을 특징으로 한다.Characterized in having a.
본 발명에 있어서, 상기 PET 소스가스를 상기 반응기 내에 도입하는 시간은 10∼15초인 것이 바람직하다.In the present invention, the time for introducing the PET source gas into the reactor is preferably 10 to 15 seconds.
또한, 상기 퍼지가스를 상기 반응기 내에 도입하는 시간은 10∼15초인 것이 바람직하다.In addition, the time for introducing the purge gas into the reactor is preferably 10 to 15 seconds.
또한, 상기 반응가스인 산소를 상기 반응기 내에 도입하는 시간도 10∼15초인 것이 바람직하다.In addition, the time for introducing the oxygen, which is the reaction gas, into the reactor is preferably 10 to 15 seconds.
이하, 본 발명의 바람직한 실시예에 대해 설명한다.Hereinafter, preferred embodiments of the present invention will be described.
우선, 화학기상 증착 반응기 내의 서셉터 상에 반도체 기판을 위치시킨다. 이어서, 상기 서셉터에 내장된 히터 또는 반응기 외부에 설치된 히터를 이용하여 상기 기판을 공정 온도인 300∼700℃ 내의 온도로 가열한다. 그 다음, 별도의 압력 조절 없이 기본 진공압(base vacuum)을 유지한 상태에서 탄탈륨 소스가스인 PET를 상기 반응기 내에 10∼15초 동안 도입한다. 원자층 증착법에서는 막의 증착속도를높이기 위해 가스 도입 주기를 빠르게 해야만 하므로 하나의 가스 공급시간이 수초 정도이지만, 가스 공급시간을 이와 같이 빠르게 변화시키게 되면 밸브의 조작에 무리가 가기 때문에 장비가 쉽게 고장이 날 염려가 있다. 따라서, 본 실시예에서는 가스 공급시간을 10∼15초 정도로 정하였다. 이어서, 기판에 흡착된 PET의 불순물을 제거하거나 균일한 원자층 형성을 목적으로 퍼지용 아르곤 가스를 반응기 내에 10∼15초 동안 도입한다. 그 후, 반응가스인 산소를 상기 반응기 내에 10∼15초 동안 도입하여 원자층 단위로 탄탈륨 산화막을 형성한 후, 상기 반응기 내부를 퍼지하기 위해 아르곤 가스를 반응기 내에 다시 10∼15초 동안 도입한다. 이와 같이 PET 도입에서 원자층단위의 탄탈륨 산화막 형성 후 퍼지공정을 2∼3회 반복한다. 이와 같이 하면 탄탈륨 산화막과 그 하부구조의 계면에서 원자층 단위로 반응이 일어나고 반응 부산물에 해당하는 탄소, 수소가 반응가스인 산소와 결합한 후 퍼지가스인 아르곤 가스와 더불어 반응기의 외부로 배출되기 때문에, 탄탈륨 산화막과 그 하부구조의 계면에 불순물이 적게 생성된다. 상기한 바와 같이 PET 도입에서 원자층단위의 탄탈륨 산화막 형성 후 퍼지공정를 반복하는 것은 원자층 증착방법과 유사하지만, 전체 막의 형성이 원자층 증착방법으로 이루어지는 것은 아니기 때문에 본 발명에서 2∼3 층의 탄탈륨 산화막 형성방법을 가성 원자층 증착방법(Pseudo Atomic Layer Deposition)이라고 칭하였다. 가성 원자층 증착방법은 반드시 2∼3회만 진행하는 것으로 제한되는 것은 아니며, 공정시간과 요구되는 막질을 고려하여 그 회수를 결정할 수 있음은 물론이다.First, a semiconductor substrate is placed on a susceptor in a chemical vapor deposition reactor. Subsequently, the substrate is heated to a temperature within a process temperature of 300 to 700 ° C. using a heater built in the susceptor or a heater installed outside the reactor. Then, PET, which is a tantalum source gas, is introduced into the reactor for 10 to 15 seconds while maintaining a base vacuum without additional pressure control. In the atomic layer deposition method, the gas introduction cycle must be fast to increase the deposition rate of the film, so a single gas supply time is several seconds. There is concern for me. Therefore, in this embodiment, the gas supply time is set to about 10 to 15 seconds. Subsequently, purging argon gas is introduced into the reactor for 10 to 15 seconds to remove impurities of PET adsorbed on the substrate or to form a uniform atomic layer. Thereafter, oxygen, which is a reaction gas, is introduced into the reactor for 10 to 15 seconds to form a tantalum oxide film in atomic layer units, and then argon gas is introduced into the reactor for 10 to 15 seconds to purge the inside of the reactor. As described above, the purge process is repeated two to three times after the formation of the tantalum oxide film on an atomic layer basis in PET introduction. In this case, the reaction occurs at the interface between the tantalum oxide film and its substructure on an atomic layer basis, and carbon and hydrogen corresponding to reaction by-products are combined with oxygen, which is a reaction gas, and then discharged outside the reactor together with argon gas, which is a purge gas. Less impurities are produced at the interface between the tantalum oxide film and its substructure. As described above, repeating the purge process after forming the tantalum oxide film at the atomic layer level in the introduction of PET is similar to the atomic layer deposition method, but since the formation of the entire film is not performed by the atomic layer deposition method, two to three layers of tantalum in the present invention are used. The oxide film formation method was called a pseudo atomic layer deposition method. The caustic atomic layer deposition method is not necessarily limited to only two or three times, and of course, the recovery time may be determined in consideration of the process time and the required film quality.
이와 같이 계면특성이 향상된 2∼3 층의 탄탈륨 산화막을 형성한 후에는, 반응기 내를 1mTorr∼100Torr 사이의 공정 압력이 되도록 감압시킨다. 그 다음, 상기 반응기 내에 탄탈륨 소스가스인 PET와 반응가스인 산소를 동시에 도입하여 본격적인 화학기상 증착공정을 진행하여 원하는 두께의 탄탈륨 산화막을 얻는다.After the two to three layers of tantalum oxide films having improved interfacial properties are formed, the reactor is depressurized to a process pressure of 1 mTorr to 100 Torr. Next, PET and tantalum source gas and oxygen as reaction gas are simultaneously introduced into the reactor to perform a full-scale chemical vapor deposition process to obtain a tantalum oxide film having a desired thickness.
본 발명에 따르면, 탄탈륨 산화막과 그 하부구조의 계면에서 탄소, 수소 등의 불순물을 현저히 줄일 수 있을 뿐 아니라 단차피복성(step coverage)이 우수한 탄탈륨 산화막을 얻을 수 있다.According to the present invention, it is possible to significantly reduce impurities such as carbon and hydrogen at the interface between the tantalum oxide film and the substructure thereof, and to obtain a tantalum oxide film having excellent step coverage.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR950002061A (en) * | 1993-06-08 | 1995-01-04 | 이기준 | Tantalum oxide thin film formation method and its application |
| KR20000015134A (en) * | 1998-08-27 | 2000-03-15 | 윤종용 | GATE ELECTRODE HAVING TiN ELECTRODE LAYER AND METHOD THEREOF |
| KR20000024715A (en) * | 1998-10-01 | 2000-05-06 | 김영환 | Method for fabricating tantalum oxidation film and method for fabricating capacitor of semiconductor device using the same |
| KR20010111448A (en) * | 2000-06-08 | 2001-12-19 | 이경수 | Method for forming a thin film |
| KR20020037293A (en) * | 2000-11-13 | 2002-05-18 | 조셉 제이. 스위니 | ATOMIC LAYER DEPOSITION OF Ta2O5 AND HIGH-K DIELECTRICS |
| JP2002305195A (en) * | 2000-12-18 | 2002-10-18 | Hynix Semiconductor Inc | Method of forming tantalum oxide film utilizing plasma atomic layer deposition method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR950002061A (en) * | 1993-06-08 | 1995-01-04 | 이기준 | Tantalum oxide thin film formation method and its application |
| KR20000015134A (en) * | 1998-08-27 | 2000-03-15 | 윤종용 | GATE ELECTRODE HAVING TiN ELECTRODE LAYER AND METHOD THEREOF |
| KR20000024715A (en) * | 1998-10-01 | 2000-05-06 | 김영환 | Method for fabricating tantalum oxidation film and method for fabricating capacitor of semiconductor device using the same |
| KR20010111448A (en) * | 2000-06-08 | 2001-12-19 | 이경수 | Method for forming a thin film |
| KR20020037293A (en) * | 2000-11-13 | 2002-05-18 | 조셉 제이. 스위니 | ATOMIC LAYER DEPOSITION OF Ta2O5 AND HIGH-K DIELECTRICS |
| JP2002305195A (en) * | 2000-12-18 | 2002-10-18 | Hynix Semiconductor Inc | Method of forming tantalum oxide film utilizing plasma atomic layer deposition method |
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