KR100453951B1 - Method for forming the Pad Oxide Layer of Semiconductor Device - Google Patents

Method for forming the Pad Oxide Layer of Semiconductor Device Download PDF

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KR100453951B1
KR100453951B1 KR10-2002-0002447A KR20020002447A KR100453951B1 KR 100453951 B1 KR100453951 B1 KR 100453951B1 KR 20020002447 A KR20020002447 A KR 20020002447A KR 100453951 B1 KR100453951 B1 KR 100453951B1
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pad oxide
oxide film
forming
heat treatment
pad
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KR10-2002-0002447A
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KR20030062047A (en
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피승호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

본 발명은 반도체 소자의 제조 공정 중 소자분리막 형성 시, 증착되는 패드산화막 형성방법에 관한 것으로, 기존의 패드산화막을 형성하던 퍼니스 타입(Furnace Type)의 열처리 방법 대신 급속 열처리(Rapid Thermal Annealing) 장비를 이용하여 패드산화막을 형성함으로써, 실리콘 웨이퍼 내에 소자 특성 균일도를 증가시킬 수 있을 뿐만 아니라 게터링 효율도 증가 시켜 반도체소자의 리프레쉬 특성을 향상시킬 수 있는 기술이다.The present invention relates to a method for forming a pad oxide film that is deposited when a device isolation layer is formed during a manufacturing process of a semiconductor device. A rapid thermal annealing device is used instead of a furnace type heat treatment method for forming a pad oxide film. By forming the pad oxide film by using the same, the uniformity of the device characteristics in the silicon wafer can be increased and the gettering efficiency can also be increased to improve the refresh characteristics of the semiconductor device.

Description

반도체소자의 패드산화막 형성방법{Method for forming the Pad Oxide Layer of Semiconductor Device}Method for forming pad oxide layer of semiconductor device

본 발명은 급속 열처리 장비를 이용해서 패드산화막을 형성하여 실리콘 웨이퍼 내에 소자 특성 균일도를 증가시킬 뿐만 아니라 게터링 효율도 증가 시켜 반도체소자의 리프레쉬 특성을 향상시키도록 하는 반도체소자의 패드산화막 형성방법에 관한 것이다.The present invention relates to a method for forming a pad oxide film of a semiconductor device to form a pad oxide film using a rapid heat treatment device to improve the refresh characteristics of the semiconductor device by increasing the gettering efficiency as well as increasing the device characteristic uniformity in the silicon wafer. will be.

일반적으로 반도체 장치에서 널리 이용되는 선택산화에 의한 소자분리 방법 중 하나인종래의 국부산화막 (LOCal Oxidation of Silicon : 이하 "LOCOS"라 한다) 공정은 소자가 형성되는 실리콘기판에 먼저 패드산화막을 성장시키고 그 위에 산화방지마스크 물질인 패드질화막을 증착한 후 마스크를 이용한 노광 및 식각공정을 거쳐 소자분리막이 형성되는 지역을 설정하고 고온에서 습식 및 건식산화방식으로 두꺼운 산화막을 성장시켜 이 산화막을 소자분리막으로 사용하는 기술이다.The conventional LOCal Oxidation of Silicon (LOCOS) process, which is one of the device isolation methods by selective oxidation, which is widely used in semiconductor devices, is first grown on a silicon substrate on which a device is formed. After depositing a pad nitride film as an anti-oxidation mask material, the area where the device isolation film is formed is formed through an exposure and etching process using a mask, and a thick oxide film is grown by wet and dry oxidation at a high temperature to convert the oxide film into a device isolation film. It is a technique to use.

상기와 같이 일반적으로 반도체소자의 제조 공정 중 산화막을 이용한 소자분리는 매우 중요하며, 소자분리막과 소자활성영역을 정의하기 위해서 진행되는 일련의 과정에서 소자분리막 패턴 형성은 패드질화막을 이용하였다.As described above, device isolation using an oxide film is very important in the process of manufacturing a semiconductor device, and a pad nitride film is used to form a device isolation pattern in a series of processes to define the device isolation layer and the device active region.

그러나, 상기 패드질화막은 소자가 형성될 실리콘 웨이퍼와의 계면에 큰 응력을 받게되고 이 응력의 크기가 과도하게 크면 실리콘 웨이퍼에 결정결함이 발생되는 문제점이 있었다.However, the pad nitride film is subjected to a large stress at the interface with the silicon wafer on which the device is to be formed, and if the magnitude of the stress is excessively large, there is a problem that crystal defects occur in the silicon wafer.

그래서, 종래에는 상기 패드질화막의 응력을 막기 위해 패드질화막 형성 이전에 퍼니스 타입(furnace type)의 열처리 방법을 이용하여 패드산화막을 형성함으로써 패드질화막에서 유발되는 응력을 완화시켰다.Thus, conventionally, in order to prevent the stress of the pad nitride film, the stress caused by the pad nitride film is alleviated by forming a pad oxide film using a furnace type heat treatment method before the pad nitride film is formed.

도 1는 종래 반도체소자의 패드산화막 형성방법에 의해 패드산화막을 형성하였을 경우 실리콘 웨이퍼의 소수 캐리어 라이프 타임 맵을 도시적으로 나타낸 사진이다.FIG. 1 is a photograph showing a minority carrier lifetime map of a silicon wafer when a pad oxide film is formed by a method of forming a pad oxide film of a conventional semiconductor device.

그런데, 도 1에 도시된 바와 같이, 종래의 퍼니스 타입(furnace type)의 열처리 방법에 의해 형성된 패드산화막은 패드질화막과 실리콘 웨이퍼와의 계면에서 발생되는 응력을 제거하는 기능 뿐 실리콘 웨이퍼의 결정 성장 조건에 따른 세가지 유형의 영역 즉, 공공 과다(vacancy-Rich)영역(A), 침입형 실리콘 과다(Interstitial Rich)영역(B), 오.에스.에프 밴드(Oxidation induced Stacking Fault : OSF)(C)의 그 특징상 후속 열공정에 따라 각기 다른 산소석출물 형성 양상을 보이는 문제점을 해결할 수 없었다.However, as shown in FIG. 1, the pad oxide film formed by the conventional furnace type heat treatment method has a function of removing stresses generated at the interface between the pad nitride film and the silicon wafer, as well as crystal growth conditions of the silicon wafer. Three types of zones: vacancy-rich zone (A), interstitial rich zone (B), and Oxidation induced stacking fault (OSF) (C). Due to its characteristics, it was not possible to solve the problem of forming different oxygen precipitates according to the subsequent thermal process.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 본 발명의 목적은 기존의 퍼니스 타입(Furnace Type)의 열처리 방법 대신 급속 열처리(Rapid Thermal Annealing) 장비를 이용하여 패드산화막을 형성함으로써, 실리콘 웨이퍼 내의 소자 특성 균일도를 증가시킬 수 있을 뿐만 아니라 게터링(Gettering) 효율도 증가 시켜 반도체소자의 리프레쉬 특성을 향상시킬 수 있도록 하는 것이 목적이다.The present invention has been made to solve the above problems, an object of the present invention is to form a pad oxide film by using a rapid thermal annealing (Rapid Thermal Annealing) equipment, instead of the conventional furnace type (Furnace type) heat treatment method, The purpose of the present invention is not only to increase the uniformity of device characteristics in a wafer but also to improve gettering efficiency to improve refresh characteristics of semiconductor devices.

도 1는 종래 반도체소자의 패드산화막 형성방법에 의해 패드산화막을 형성하였을 경우 실리콘 웨이퍼의 소수 캐리어 라이프 타임 맵을 도시적으로 나타낸 사진이다.FIG. 1 is a photograph showing a minority carrier lifetime map of a silicon wafer when a pad oxide film is formed by a method of forming a pad oxide film of a conventional semiconductor device.

도 2은 본 발명의 실시예에 따른 반도체소자의 패드산화막 형성방법에 의해 형성된 패드산화막을 개략적으로 나타낸 단면도이다.2 is a cross-sectional view schematically illustrating a pad oxide film formed by a method of forming a pad oxide film of a semiconductor device according to an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 반도체소자의 패드산화막 형성방법에 의해 패드산화막을 형성하였을 경우 실리콘 웨이퍼의 소수 캐리어 라이프 타임 맵을 도시적으로 나타낸 사진이다.3 is a photograph showing a minority carrier life time map of a silicon wafer when a pad oxide film is formed by a method of forming a pad oxide film of a semiconductor device according to an exemplary embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 실리콘 웨이퍼 2 : 패드산화막1 silicon wafer 2 pad oxide film

3 : 패드질화막 a : 소자활성영역3: pad nitride film a: device active region

b : 소자분리영역b: device isolation area

상기 목적을 달성하기 위하여, 본 발명은 실리콘 웨이퍼 표면 전체에 급속 열처리 장비를 이용하여 패드산화막을 형성한 후 그 상부에 패드질화막을 적층하는 단계와, 상기 패드질화막 전면에 감광막을 도포하고 노광 및 현상공정을 통해 감광막 패턴을 형성한 후 이를 식각마스크로 패드질화막과 패드산화막을 식각하여 소자활성영역과 소자분리영역을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 패드산화막 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the step of forming a pad oxide film on the entire surface of the silicon wafer using a rapid heat treatment equipment, and then laminating a pad nitride film on the top, applying a photosensitive film on the entire surface of the pad nitride film, exposure and development And forming a device active region and a device isolation region by etching the pad nitride layer and the pad oxide layer using an etch mask after forming the photoresist pattern through the process. .

바람직하게 본 발명은 상기 패드산화막 형성 시, 급속 열처리 장비의 온도를 10℃/sec 이상의 속도로 상승시키며, 패드산화막은 1000℃ 이상 분위기에서 형성하고, 패드산화막을 형성한 후엔, 급속 열처리 장비의 온도를 30℃/sec이상의 속도로 강하시키는 것을 특징으로 한다.Preferably, when the pad oxide film is formed, the temperature of the rapid heat treatment equipment is increased at a rate of 10 ° C./sec or more, and the pad oxide film is formed in an atmosphere of 1000 ° C. or more, and after forming the pad oxide film, the temperature of the rapid heat treatment equipment is It is characterized by dropping at a rate of 30 ℃ / sec or more.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2은 본 발명의 실시예에 따른 반도체소자의 패드산화막 형성방법에 의해 형성된 패드산화막을 개략적으로 나타낸 단면도이다.2 is a cross-sectional view schematically illustrating a pad oxide film formed by a method of forming a pad oxide film of a semiconductor device according to an embodiment of the present invention.

도 2에 도시된 바와 같이, 실리콘 웨이퍼(1) 표면 전체에 급속 열처리 장비를 이용하여 패드산화막(2)을 형성한 후, 그 상부에 패드질화막(3)을 적층한다.As shown in FIG. 2, after the pad oxide film 2 is formed on the entire surface of the silicon wafer 1 by using rapid heat treatment equipment, the pad nitride film 3 is laminated thereon.

이때, 상기 패드산화막(2) 형성 시, 급속 열처리 장비의 온도를 10℃/sec ~ 30℃/sec 이상의 속도로 상승시켜, 1000℃~ 1250℃ 이상의 온도에서 패드산화막(2)을 형성한 후, 급속 열처리 장비의 온도를 30℃/sec ~ 70℃/sec 이상의 속도로 강하시킨다.At this time, when the pad oxide film 2 is formed, the temperature of the rapid heat treatment equipment is increased at a rate of 10 ° C./sec to 30 ° C./sec or more, and after the pad oxide film 2 is formed at a temperature of 1000 ° C. to 1250 ° C. or more, The temperature of the rapid heat treatment equipment is lowered at a rate of 30 ° C./sec to 70 ° C./sec or more.

또한, 상기 패드산화막(2)을 형성하기 위한 급속 열처리 장비의 온도 상승 시에는 질소 또는 아르곤 가스 분위기에서 진행하거나, 산소가스와 질소 또는 아르곤가스 중 적어도 어느 하나 이상이 혼합된 혼합가스 분위기에서 진행하며, 패드산화막(2) 형성 시에는 산소가스와 질소 또는 아르곤가스 중 적어도 어느 하나 이상이 혼합된 혼합가스 분위기에서 형성하거나 산소가스 분위기 내에서 형성한다.In addition, when the temperature of the rapid heat treatment equipment for forming the pad oxide film 2 rises in a nitrogen or argon gas atmosphere, or at least any one of oxygen gas and nitrogen or argon gas is mixed in a mixed gas atmosphere When the pad oxide film 2 is formed, at least one of oxygen gas and nitrogen or argon gas is formed in a mixed gas atmosphere or in an oxygen gas atmosphere.

그리고, 상기 패드질화막(3) 전면에 감광막(미도시함)을 도포하고 노광 및 현상공정을 통해 감광막 패턴(미도시함)을 형성한 후, 그를 식각마스크로 패드질화막(3)과 패드산화막(2)을 식각하여 소자활성영역(a)과 소자분리영역(b)을 형성한다.Then, a photoresist film (not shown) is applied to the entire surface of the pad nitride film 3, and a photoresist pattern (not shown) is formed through an exposure and development process, and then, the pad nitride film 3 and the pad oxide film (such as an etch mask) are used. 2) is etched to form the device active region a and the device isolation region b.

도 3은 본 발명의 실시예에 따른 반도체소자의 패드산화막 형성방법에 의해 패드산화막을 형성하였을 경우 실리콘 웨이퍼의 소수 캐리어 라이프 타임 맵을 도시적으로 나타낸 사진이다.3 is a photograph showing a minority carrier life time map of a silicon wafer when a pad oxide film is formed by a method of forming a pad oxide film of a semiconductor device according to an exemplary embodiment of the present invention.

일반적으로 실리콘 웨이퍼 내의 공공의 농도는 온도에 지수함수적으로 비례하나 온도가 내려가면 증가된 공공의 농도가 원상태의 농도로 돌아오게되는데 이때, 고온에서의 농도를 저온까지 일정하게 유지하는 방법이 급속열처리 방법 즉, 급속냉각이다.In general, the concentration of vacancy in the silicon wafer is exponentially proportional to temperature, but when the temperature decreases, the concentration of vacancy returns to its original concentration. Heat treatment method, that is, rapid cooling.

그럼으로, 도 3에 도시된 바와 같이, 본 발명의 급속 열처리 장비를 이용하여 패드산화막(미도시함) 형성 시, 고온에서 저온으로 온도를 낮출 때 공공의 농도가 열역학적인 평행농도에 도달할 시간적 여유 없이 급속히 냉각하게 되면 그 농도를 상당한 정도 유지하게 되며, 특히, 실리콘 웨이퍼 내에 있는 침입형 산소 원자는 공공과 인력(attractive force)이 작용하여 공공의 확산을 통하여 침입형 실리콘과 합쳐져 소멸되거나 확산되어 실리콘 웨이퍼 표면을 통하여 빠져나가는 것을 억제하게 된다.Thus, as shown in Figure 3, when forming a pad oxide film (not shown) using the rapid heat treatment equipment of the present invention, when the temperature is lowered from high temperature to low temperature when the concentration of the pore reaches a thermodynamic parallel concentration Rapid cooling without room maintains its concentration to a certain extent. Particularly, the invasive oxygen atoms in the silicon wafer act as vacant and attractive forces, which are combined with the invasive silicon through the diffusion of the vacancies and disappear or diffuse. Escape through the silicon wafer surface is suppressed.

그 결과, 실리콘 웨이퍼의 결정 성장 조건에 따른 세가지 유형의 영역 즉, 공공 과다(vacancy-Rich)영역, 침입형 실리콘 과다(Interstitial Rich)영역, 오.에스.에프 밴드(Oxidation induced Stacking Fault : OSF) 내에 존재하는 산소석출물의 불균일도가 제거되어 소자 특성 균일도가 증가된다.As a result, three types of regions, vacancy-rich regions, interstitial rich regions, and Oxidation induced stacking faults (OSFs) according to the crystal growth conditions of the silicon wafer. The nonuniformity of the oxygen precipitates present therein is removed to increase device characteristic uniformity.

따라서, 본 발명에 따른 반도체소자의 소자분리막 형성방법을 이용하게 되면 기존의 퍼니스 타입(Furnace Type)의 열처리 방법 대신 급속 열처리(Rapid Thermal Annealing) 장비를 이용하여 패드산화막을 형성함으로써, 패드질화막과 실리콘 웨이퍼와의 계면에서 발생되는 응력을 제거할 뿐만 아니라 실리콘 웨이퍼의 결정 성장 조건에 따른 세가지 유형의 영역 즉, 공공 과다(vacancy-Rich)영역, 침입형 실리콘 과다(Interstitial Rich)영역, 오.에스.에프 밴드(Oxidation induced Stacking Fault : OSF) 내에 존재하는 산소석출물의 불균일도가 제거되어 소자 특성 균일도를 증가시킬 수 있는 효과가 있다.Therefore, when the device isolation film forming method of the semiconductor device according to the present invention is used, the pad nitride film and the silicon are formed by forming a pad oxide film using a rapid thermal annealing device instead of the conventional furnace type heat treatment method. In addition to eliminating the stress generated at the interface with the wafer, three types of regions depending on the crystal growth conditions of the silicon wafer, namely, vacancy-rich regions, interstitial rich regions, and O.S. Oxidation induced stacking fault (OSF) is eliminated the non-uniformity of the oxygen precipitates present in the OSF has the effect of increasing the device characteristic uniformity.

또한, 상기 산소석출물이 충분한 깊이 이하에 형성될 경우 공정 진행 중 도입되는 불순물의 게터링(Gettering) 시트(site) 역할을 하여 게터링 효율을 증가 시킴으로써 반도체소자의 리프레쉬 특성을 향상시키는 효과가 있다.In addition, when the oxygen precipitate is formed at a sufficient depth or less, the gettering sheet serves as a gettering site of impurities introduced during the process, thereby increasing the gettering efficiency, thereby improving the refresh characteristics of the semiconductor device.

Claims (4)

실리콘 웨이퍼 표면 전체에 급속 열처리 장비를 이용하여 패드산화막을 형성한 후 그 상부에 패드질화막을 적층하는 단계와;Forming a pad oxide film on the entire surface of the silicon wafer using a rapid heat treatment apparatus, and then depositing a pad nitride film thereon; 상기 패드질화막 전면에 감광막을 도포하고 노광 및 현상공정을 통해 감광막 패턴을 형성한 후 이를 식각마스크로 패드질화막과 패드산화막을 식각하여 소자활성영역과 소자분리영역을 형성하는 단계를 포함하여 구성되되,Forming a device active region and a device isolation region by coating a photoresist on the entire surface of the pad nitride layer, forming a photoresist pattern through an exposure and development process, and then etching the pad nitride layer and the pad oxide layer with an etch mask. 상기 패드산화막을 형성하기 위한 급속 열처리 장비의 온도 상승은 산소가스와 질소 또는 아르곤가스 중 적어도 어느 하나 이상이 혼합된 분위기에서 진행하거나 산소가스 단독 분위기에서 진행하고,The temperature increase of the rapid heat treatment equipment for forming the pad oxide film proceeds in an atmosphere in which at least one or more of oxygen gas and nitrogen or argon gas is mixed or in an oxygen gas alone atmosphere, 패드산화막 형성 후, 급속 열처리 장비의 온도를 30℃/sec이상의 속도로 강하시키는 것을 특징으로 하는 반도체소자의 패드산화막 형성방법.After the pad oxide film is formed, the temperature of the rapid heat treatment equipment is lowered at a rate of 30 ℃ / sec or more pad oxide film forming method of a semiconductor device. 제 1항에 있어서, 상기 패드산화막 형성 시, 급속 열처리 장비의 온도를 10℃/sec 이상의 속도로 질소 또는 아르곤 가스 분위기에서 상승시키는 것을 특징으로 하는 반도체소자의 패드산화막 형성방법.The method of claim 1, wherein, when the pad oxide film is formed, the temperature of the rapid heat treatment equipment is increased in a nitrogen or argon gas atmosphere at a rate of 10 ° C./sec or more. 삭제delete 삭제delete
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980015330A (en) * 1996-08-21 1998-05-25 김주용 Device isolation method of semiconductor device
KR19990017051A (en) * 1997-08-21 1999-03-15 윤종용 Device Separation Method of Semiconductor Device
US6040214A (en) * 1998-02-19 2000-03-21 International Business Machines Corporation Method for making field effect transistors having sub-lithographic gates with vertical side walls
US6461529B1 (en) * 1999-04-26 2002-10-08 International Business Machines Corporation Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980015330A (en) * 1996-08-21 1998-05-25 김주용 Device isolation method of semiconductor device
KR19990017051A (en) * 1997-08-21 1999-03-15 윤종용 Device Separation Method of Semiconductor Device
US6040214A (en) * 1998-02-19 2000-03-21 International Business Machines Corporation Method for making field effect transistors having sub-lithographic gates with vertical side walls
US6461529B1 (en) * 1999-04-26 2002-10-08 International Business Machines Corporation Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme

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