JPS6261353A - Manufacture of complementary mos semiconductor element - Google Patents
Manufacture of complementary mos semiconductor elementInfo
- Publication number
- JPS6261353A JPS6261353A JP60199345A JP19934585A JPS6261353A JP S6261353 A JPS6261353 A JP S6261353A JP 60199345 A JP60199345 A JP 60199345A JP 19934585 A JP19934585 A JP 19934585A JP S6261353 A JPS6261353 A JP S6261353A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- resist
- well
- silicon substrate
- protect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は相補型ＭＯＳ半導体の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a complementary MOS semiconductor.
（従来の技術）
第２図（ａ）〜（ｆ）は、従来の一般的なＰウェルタイ
プの相補型ＭＯＳ半導体素子の製造方法を工程層に説明
するものであり、簡略化のためＮ型ＭＯ３部分のみを示
しである。(Prior Art) Figures 2(a) to 2(f) explain a conventional general P-well type complementary MOS semiconductor device manufacturing method in terms of process layers. Only the MO3 portion is shown.
先づ（ａ）において、シリコン基板２１に５０００〜１
００００Ａの厚い酸化膜２２を熱成長させ、ホトエツチ
ングによりＰウェル部２３とその後の工程で使用するマ
スク合わせ用パターン２４を穿設し、さらに均一なイオ
ン注入を得るため４００〜８００Ａの薄い酸化膜（プロ
テクト酸化膜）２５を成長させた後、イオン注入法でＰ
型の不純物を注入する。２６はこのときに注入されたＰ
型不純物を示す。In step (a), 5000 to 1 is applied to the silicon substrate 21.
A thick oxide film 22 of 0000A is thermally grown, a P-well portion 23 and a pattern 24 for mask alignment used in subsequent steps are formed by photoetching, and a thin oxide film 22 of 400-800A is grown to obtain more uniform ion implantation. After growing a protective oxide film (25), P
Inject mold impurities. 26 is the P injected at this time.
Indicates type impurities.
次にｏ３）に示すように、Ｐ型不純物２６を拡散させＰ
ウェル層２６′を形成するために、１１００〜１２００
℃で３〜１０時間の熱処理を行う。２７はこの際シリコ
ン基板２１が酸化することにより生ずる段差部であり、
後述する工程におけるパターン合わせの基準として使用
される。Next, as shown in o3), the P-type impurity 26 is diffused and P
1100-1200 to form the well layer 26'.
Heat treatment is performed at ℃ for 3 to 10 hours. Reference numeral 27 denotes a step portion that is generated when the silicon substrate 21 is oxidized;
It is used as a reference for pattern matching in the process described later.
その後、酸化膜２２を全面除去し、４００〜５ｏｏｊ：
、、の薄い酸化膜（パッド酸化膜）２８を成長させた電
子の断面を示したものが（ｅ）である。After that, the oxide film 22 is completely removed, and 400~5ooj:
(e) shows a cross section of electrons grown in the thin oxide film (pad oxide film) 28 of , .
さらに、ＬＯＣＯＳ工程において使用する窒化膜２９を
厚さ１５００〜３０００Ａに成長させ、ホトエツチング
により所定のパターンを形成する。Further, a nitride film 29 used in the LOCOS process is grown to a thickness of 1500 to 3000 Å, and a predetermined pattern is formed by photoetching.
この際ＰウェルＭ２６′との位置合わせは前記シリコン
基板段差部２７を光学的に検出して、合わせ一ギークパ
ターンエツジ３０との間隔ｂ 、 ｂ’が等しぐなるよ
うに調整しながら行われる。しかる後レジスト３１をマ
スクとして窒化膜２９をエツチング除去する。このとき
の状態を示したものが（由である。。At this time, alignment with the P-well M26' is performed by optically detecting the silicon substrate step portion 27 and adjusting the distances b and b' from the alignment geek pattern edge 30 to be equal. . Thereafter, the nitride film 29 is removed by etching using the resist 31 as a mask. The state at this time is (Yu).
そして、レジスト３１を・除去した後、酸化処理を施し
くｅ）に示すごとくフィールド酸化膜３２を形成する。After removing the resist 31, oxidation treatment is performed to form a field oxide film 32 as shown in e).
さらに、窒化膜２９及び酸化膜２８の除ゴ（、ゲート酸
化等通常の工程処理を経て、電極用金属配線を行ったも
のが（ｆ）に示される。図中、３３はソース拡散層、３
４はドレイン拡散層、３５はゲート酸化膜、３６はゲー
トポリシリコン、３７はＰウェル電極、３８はソース電
極、３９はドレイン電極、４０はゲート電極を示す。Further, the nitride film 29 and the oxide film 28 have been removed (and gate oxidized, etc.) and metal wiring for electrodes has been formed, as shown in FIG.
4 is a drain diffusion layer, 35 is a gate oxide film, 36 is a gate polysilicon, 37 is a P-well electrode, 38 is a source electrode, 39 is a drain electrode, and 40 is a gate electrode.
（発明が解決しようとする問題点）
しかし・上記の従来方法においては、厚い酸化膜形成工
程、プロテクト酸化工程、ノぐラド酸化工程等多くの熱
酸化工程が含まれてお９−、これらの工程によって形成
される酸化膜はシリコン基板に対して熱膨張率差に基因
する圧縮応力を与える。(Problems to be Solved by the Invention) However, the above-mentioned conventional method includes many thermal oxidation steps such as a thick oxide film formation step, a protect oxidation step, and a no-glado oxidation step. The oxide film formed by the process applies compressive stress to the silicon substrate due to the difference in coefficient of thermal expansion.
そして、この圧縮応力は酸化膜厚が厚くなるほど増大し
、ウェハのソリやスリップ等の欠陥を発生させる原因と
なっている。This compressive stress increases as the oxide film becomes thicker, causing defects such as warping and slipping of the wafer.
さらに、深い拡散層を必要とするＰウェル形成工程でも
、高温長時間の熱処理が行われるため、厚い酸化膜とシ
リコン基板との界面付近に生ずる圧縮応力はウェハの欠
陥原因となり易い。Furthermore, even in the P-well formation process that requires a deep diffusion layer, heat treatment is performed at high temperatures and for a long time, so compressive stress generated near the interface between the thick oxide film and the silicon substrate is likely to cause defects in the wafer.
この発明は似上述べた熱処理時に発生する圧縮応力が原
因となっているウニへのソリやスリップ等の欠陥を防止
することを目的とする。The object of the present invention is to prevent defects such as warping and slipping of sea urchins caused by compressive stress generated during heat treatment as described above.
（問題点を解決するための手段）
この発明は相補型ＭＯＳ半導体素子の製造方法び合わせ
マーク部の前記レジストを除去する工程注入する工程と
、合わせマーク部以外に再度レジストを形成し、エツチ
ングにより合わせマーク部に段差を形成する工程全類に
施し、前記プロテクト酸化膜をＬＯＣＯＳ用のパッド酸
化膜として再使用することを特徴とするものである。(Means for Solving the Problems) The present invention provides a method for manufacturing a complementary MOS semiconductor device, a step of removing the resist in the alignment mark portion, a step of implanting, forming a resist again in areas other than the alignment mark portion, and etching. This method is characterized in that it is applied to all the steps of forming a step in the alignment mark portion, and the protect oxide film is reused as a pad oxide film for LOCOS.
（作 用）
この発明では、従来方法のように初期工程において厚い
酸化膜を形成する仁となく、さらにプロテクト酸化膜を
パッド酸化膜として再使用するため、シリコン基板に生
ずる圧縮応力を可及的に抑１ｌｊ１丈ることかでき、ウ
ェハのソリやスリップ等を防止できる。(Function) In this invention, unlike the conventional method, there is no need to form a thick oxide film in the initial process, and since the protect oxide film is reused as a pad oxide film, the compressive stress generated in the silicon substrate can be reduced as much as possible. It is possible to reduce the length of the wafer, thereby preventing warping and slipping of the wafer.
（実施例）
以下、図面に基づいてこの発明を説明する。第１図（ａ
）〜（ｅ）はこの発明の製造方法をＰウェルタイプにつ
いて工程順に説明するものである。(Example) The present invention will be described below based on the drawings. Figure 1 (a
) to (e) explain the manufacturing method of the present invention for a P-well type in the order of steps.
先づ（ａ）において、シリコン基板１に４００〜８００
λの比較的薄い酸化膜（プロテクト酸化膜）２を成長さ
せ、さらにレジスト３を積層し、次いでＰウェル部４及
び合わせマーク部５の前記レジスト３を除去し、残され
たレジスト３をマスクとしてＰ型不純物６をイオン注入
する。In step (a), 400 to 800
A relatively thin oxide film (protective oxide film) 2 of λ is grown, a resist 3 is further laminated, and then the resist 3 in the P well part 4 and alignment mark part 5 is removed, and the remaining resist 3 is used as a mask. P-type impurity 6 is ion-implanted.
続いてレジスト７を再度コーティングし、合わせマーク
部５のみを開孔ｌ〜たものが（ｂ）である。この状態か
ら通常のエツチシダ法を用いて、酸化膜２とシリフン基
板１を深さ５００〜５０００Ａにエツチング除去し、合
わせマーク８を形成する。Subsequently, the resist 7 was coated again, and only the alignment mark portions 5 were opened, as shown in (b). From this state, the oxide film 2 and silicone substrate 1 are etched away to a depth of 500 to 5000 Å using a normal etching process to form alignment marks 8.
その後、Ｐウェル用のレジスト３及び再＃コーティング
レジスト７を全面除去したものが（ｅ）である次に、Ｎ
、あるいはＡｒ等の不活性ガス雰囲気中で熱処理が行わ
れＰウェル層９が形成される。（ｄ）に示されるように
、酸化膜２の成長は起こらず拡散のみが進行する。After that, the resist 3 for P well and the re-coating resist 7 are completely removed, as shown in (e).
Alternatively, heat treatment is performed in an atmosphere of an inert gas such as Ar, and the P well layer 9 is formed. As shown in (d), the growth of the oxide film 2 does not occur and only diffusion progresses.
その後、前記酸化膜（プロテクト酸化膜）２をパッド酸
化膜として利用し、ＬＯＣＯＳ工程において使用する厚
さ１５００〜３ｏｏｏＸの窒化膜１０を成長させ、ホト
エツチングにより所定のパターンを形成する。この際Ｐ
ウェル層９との位置合わせは、前記従来方法と同様に行
われ、この状態を示したものが（ｅ）である。Thereafter, using the oxide film (protection oxide film) 2 as a pad oxide film, a nitride film 10 with a thickness of 1,500 to 300X is grown to be used in the LOCOS process, and a predetermined pattern is formed by photoetching. At this time P
Alignment with the well layer 9 is performed in the same manner as in the conventional method, and this state is shown in (e).
（ｅ）以後のフィールド酸化膜形成、電極用８を属配線
等の工程については前記第２図の（ｅ）及び（ｆ）と同
一となる。(e) The subsequent steps of forming a field oxide film, forming electrodes 8 and metal wiring, etc. are the same as those in (e) and (f) of FIG. 2 above.
（発明の効果）
以上説明したように本発明の製造方法によれば、Ｐある
いはＮウェル形成工程において厚い酸化膜の代替として
レジストを用いたこと、及びイオン注入用のプロテクト
酸化膜をｌ、０ＣＯ８用のパッド醸化膜として再使用し
たことによって、２段の熱処理工程を不要とし、シリコ
ン基板に生ずる圧縮応力に基因するウェハのソリやスリ
ップ等の発生を防止し得、さらに工程の削減も可能とな
る。(Effects of the Invention) As explained above, according to the manufacturing method of the present invention, a resist is used as a substitute for a thick oxide film in the P or N well formation process, and a protect oxide film for ion implantation is By reusing it as a pad-enhancing film, it is possible to eliminate the need for a two-stage heat treatment process, prevent warping and slipping of the wafer caused by compressive stress generated in the silicon substrate, and further reduce the number of processes. becomes.
第１図（ａ）〜（ｅ）は本発明の製造方法を工程順に示
す部分断面図、第２図（ａ）〜（ｆ）は従来の製造方法
を工程順に示す部分断面図である。
２・・・プロテクト酸化膜、９・・・Ｐウェル、臂、２
２・・・厚い酸化膜、２５・・・プロデクト酸イヒ膜、
２６′・Ｐウェル層、２８・パッド酸ｆ１−膜、３２・
・・フィールド酸化膜。
特許出願人 沖電気工業株式会社
１３ レレストFIGS. 1(a) to (e) are partial cross-sectional views showing the manufacturing method of the present invention in the order of steps, and FIGS. 2(a) to (f) are partial cross-sectional views showing the conventional manufacturing method in the order of steps. 2...Protect oxide film, 9...P well, arm, 2
2...Thick oxide film, 25...Prodectic acid Ichi film,
26'・P well layer, 28・Pad acid f1- film, 32・
...Field oxide film. Patent applicant Oki Electric Industry Co., Ltd. 13 Rerest
Claims (1)
順に形成し、次いでＰあるいはＮウェル部及び合わせマ
ーク部の前記レジストを除去する工程と、残された前記
レジストをマスクとし前記プロテクト酸化膜を通してＰ
あるいはＮウェル形成用の不純物を注入する工程と、合
わせマーク部以外に再度レジストを形成し、エッチング
により合わせマーク部に段差を形成する工程を順に施し
、前記プロテクト酸化膜をＬＯＣＯＳ用のパッド酸化膜
として再使用し、その後の酸化処理及び電極形成を行う
ことを特徴とする相補型ＭＯＳ半導体素子の製造方法。A step of forming a thin protect oxide film and a resist on a silicon substrate in this order, then removing the resist in the P or N well area and the alignment mark area, and using the remaining resist as a mask, applying P through the protect oxide film.
Alternatively, the process of implanting impurities for N-well formation, forming a resist again in areas other than the alignment mark area, and forming a step in the alignment mark area by etching are sequentially performed, and the protect oxide film is replaced with a pad oxide film for LOCOS. 1. A method for manufacturing a complementary MOS semiconductor device, characterized in that the device is reused as a MOS semiconductor device, and then subjected to oxidation treatment and electrode formation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60199345A JPS6261353A (en) | 1985-09-11 | 1985-09-11 | Manufacture of complementary mos semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60199345A JPS6261353A (en) | 1985-09-11 | 1985-09-11 | Manufacture of complementary mos semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6261353A true JPS6261353A (en) | 1987-03-18 |
Family
ID=16406224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60199345A Pending JPS6261353A (en) | 1985-09-11 | 1985-09-11 | Manufacture of complementary mos semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6261353A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002368147A (en) * | 2001-04-04 | 2002-12-20 | Internatl Business Mach Corp <Ibm> | Manufacturing method for semiconductor device having deep sub-collector region |
| JP2007103472A (en) * | 2005-09-30 | 2007-04-19 | Toshiba Corp | Semiconductor integrated circuit device and its manufacturing method |
| JP2007194497A (en) * | 2006-01-20 | 2007-08-02 | Fujifilm Corp | Semiconductor device manufacturing method, and solid-state imaging element manufacturing method using same |
| US20100035388A1 (en) * | 2008-08-05 | 2010-02-11 | Choi Kee-Joon | Method for fabricating semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147179A (en) * | 1975-06-12 | 1976-12-17 | Fujitsu Ltd | Method of munufacturing of semiconductor device |
| JPS594154A (en) * | 1982-06-30 | 1984-01-10 | Nec Corp | Manufacture of semiconductor device |
-
1985
- 1985-09-11 JP JP60199345A patent/JPS6261353A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147179A (en) * | 1975-06-12 | 1976-12-17 | Fujitsu Ltd | Method of munufacturing of semiconductor device |
| JPS594154A (en) * | 1982-06-30 | 1984-01-10 | Nec Corp | Manufacture of semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002368147A (en) * | 2001-04-04 | 2002-12-20 | Internatl Business Mach Corp <Ibm> | Manufacturing method for semiconductor device having deep sub-collector region |
| JP2007103472A (en) * | 2005-09-30 | 2007-04-19 | Toshiba Corp | Semiconductor integrated circuit device and its manufacturing method |
| US7943478B2 (en) | 2005-09-30 | 2011-05-17 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method |
| JP4718961B2 (en) * | 2005-09-30 | 2011-07-06 | 株式会社東芝 | Semiconductor integrated circuit device and manufacturing method thereof |
| JP2007194497A (en) * | 2006-01-20 | 2007-08-02 | Fujifilm Corp | Semiconductor device manufacturing method, and solid-state imaging element manufacturing method using same |
| US20100035388A1 (en) * | 2008-08-05 | 2010-02-11 | Choi Kee-Joon | Method for fabricating semiconductor device |
| US8338281B2 (en) * | 2008-08-05 | 2012-12-25 | Magnachip Semiconductor, Ltd. | Method for fabricating semiconductor device |
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