KR100385227B1 - 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법 - Google Patents
구리 다층 배선을 가지는 반도체 장치 및 그 형성방법 Download PDFInfo
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- KR100385227B1 KR100385227B1 KR10-2001-0006812A KR20010006812A KR100385227B1 KR 100385227 B1 KR100385227 B1 KR 100385227B1 KR 20010006812 A KR20010006812 A KR 20010006812A KR 100385227 B1 KR100385227 B1 KR 100385227B1
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- copper
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 133
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 133
- 239000010949 copper Substances 0.000 title claims abstract description 133
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000004888 barrier function Effects 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 230000009977 dual effect Effects 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 136
- 239000011229 interlayer Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 10
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 2
- 238000010790 dilution Methods 0.000 claims 1
- 239000012895 dilution Substances 0.000 claims 1
- 238000005498 polishing Methods 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (18)
- 층간 절연막에 의해 분리되며 인접하는 적어도 두 층의 금속 배선 각각이 구리층을 포함하도록 이루어지는 반도체 장치에 있어서,하층 금속 배선과 상층 금속 배선을 전기적으로 접속시키는 비아 콘택과 상기 하층 금속 배선이 접하는 계면이 상기 하층 금속 배선 쪽으로 움푹하게 들어간 홈을 이루도록 형성되며,상기 계면의 중심부인 상기 홈 저면에는 베리어층이 형성되고,상기 계면 주변부인 상기 홈 측면에는 비아 콘택의 구리층과 하층 금속 배선의 구리층이 직접 접속되는 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 계면의 주변부는 상기 비아 콘택의 측벽과 상기 하층 금속 배선이 만나는 코너 부분인 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 홈의 상부 폭이 상기 층간 절연막에 형성되는 비아 콘택 홀의 하부 폭보다 큰 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 상층 금속 배선은 상기 층간 절연막 상부의 그루브에 형성되고, 상기 비아 콘택은 상기 그루브의 일부 영역에 형성되는 듀얼 다마신 구조로 이루어지는 것을 특징으로 하는 반도체 장치.
- 제 4 항에 있어서,상기 베리어층은 상기 상층 금속 배선의 저면과 측면 및 상기 비아 콘택의 측면에 형성된 베리어층과 동일한 베리어층으로 형성된 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서,상기 하층 금속 배선과 상기 층간 절연막 사이에 부도체 베리어막이 더 구비되는 것을 특징으로 하는 반도체 장치.
- 회로 소자 및 절연막 패턴이 형성된 기판에 하층 구리 배선을 형성하는 단계,상기 하층 구리 배선 위로 층간 절연막을 적층하는 단계,상기 층간 절연막을 패터닝하여 비아 콘택 홀을 형성함으로써 하층 구리 배선 일 부분을 노출시키는 단계,상기 하층 구리 배선의 일 부분을 식각하여 하층 구리 배선에 홈을 형성하는 단계,상기 홈이 형성된 결과물 기판에 베리어층을 적층하되, 상기 홈의 측벽에는 베리어층이 적층되지 않도록 하는 단계 및상기 베리어층이 형성된 결과물 기판에 구리층을 적층하여 상기 홈을 포함하여 상기 비아 콘택 홀을 채우는 비아 콘택을 형성하는 단계를 구비하여 이루어지는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 7 항에 있어서,상기 하층 구리 배선 위에 상기 층간 절연막을 형성하기 전에 부도체 베리어막을 형성하는 단계를 더 구비하고,상기 비아 콘택 홀을 형성하는 단계에서 상기 베리어막에 대한 식각도 함께 이루어지는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 7 항에 있어서,상기 홈을 형성하는 단계에서 상기 홈의 깊이는 상기 비아 콘택 홀의 폭의 25% 이상으로 형성하는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 7 항에 있어서,상기 홈은 상기 하층 구리 배선에 대한 습식 식각을 통해 상기 층간 절연막에 대해 언더 컷을 이루도록 형성하는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 7 항에 있어서,상기 베리어층은 탄탈륨 또는 탄탈륨 질화막으로 이루어지는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 7 항에 있어서,상기 베리어층은 스퍼터링 방법으로 이루어지는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 7 항에 있어서,상기 구리층을 적층하여 비아 콘택을 형성하는 단계는 상기 베리어층 위로 구리 시드층을 형성하는 단계와 상기 시드층 위에 구리 벌크층을 형성하여 상기 비아 콘택 홀을 채우는 단계를 구비하여 이루어지는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 13 항에 있어서,상기 시드층은 CVD(Chemical Vapor Deposition)로 형성하고, 상기 벌크층은 전기도금(electroplating)법을 사용하여 형성하는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 7 항에 있어서,상기 비아 콘택 홀을 형성하는 단계 전에 상기 층간 절연막 상부에 패터닝을 통해 그루브를 형성하는 단계가 더 구비되고,상기 비아 콘택 홀은 상기 그루브와 적어도 일부 영역에서 겹치게 형성되는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 15 항에 있어서,상기 층간 절연막 상면에 쌓인 상기 구리층과 상기 베리어층을 제거하여 상기 층간 절연막을 드러내고 상기 홈을 포함하는 상기 비아 콘택 홀과 상기 그루브에만 상기 구리층을 남기는 단계가 더 구비되는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 16 항에 있어서,상기 구리층과 상기 베리어층을 제거하기 위해 CMP(Chemical Mechanical Polishing) 방법을 사용하는 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
- 제 7 항에 있어서,상기 하부 구리 배선을 식각하는 단계는 희석수에 대한 질산의 몰비가 1이하인 것을 특징으로 하는 다층 배선을 가진 반도체 장치 형성 방법.
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KR10-2001-0006812A KR100385227B1 (ko) | 2001-02-12 | 2001-02-12 | 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법 |
TW090116243A TW508726B (en) | 2001-02-12 | 2001-07-03 | Semiconductor device having multi-layer copper line and method of forming the same |
US10/067,342 US6548905B2 (en) | 2001-02-12 | 2002-02-07 | Semiconductor device having multi-layer copper line and method of forming the same |
JP2002033534A JP2002246467A (ja) | 2001-02-12 | 2002-02-12 | 半導体装置及びその形成方法 |
US10/338,908 US6884710B2 (en) | 2001-02-12 | 2003-01-09 | Semiconductor device having multi-layer copper line and method of forming same |
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KR10-2001-0006812A KR100385227B1 (ko) | 2001-02-12 | 2001-02-12 | 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7482684B2 (en) | 2005-11-25 | 2009-01-27 | Samsung Electronics Co., Ltd. | Semiconductor device with a dopant region in a lower wire |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002017693A1 (fr) * | 2000-08-18 | 2002-02-28 | Mitsubishi Denki Kabushiki Kaisha | Substrat d'installation, procede de montage d'un tel substrat et douille d'ampoule mettant en oeuvre ledit substrat |
KR100457044B1 (ko) | 2002-09-25 | 2004-11-10 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
KR100967199B1 (ko) * | 2002-12-28 | 2010-07-05 | 매그나칩 반도체 유한회사 | 반도체 소자 금속 배선 및 그의 제조 방법 |
US7215361B2 (en) | 2003-09-17 | 2007-05-08 | Micron Technology, Inc. | Method for automated testing of the modulation transfer function in image sensors |
US6861686B2 (en) * | 2003-01-16 | 2005-03-01 | Samsung Electronics Co., Ltd. | Structure of a CMOS image sensor and method for fabricating the same |
US20040152295A1 (en) * | 2003-02-03 | 2004-08-05 | International Business Machines Corporation | Sacrificial metal liner for copper |
JP2011154380A (ja) * | 2003-03-20 | 2011-08-11 | Toshiba Mobile Display Co Ltd | 表示装置の形成方法 |
JP4581485B2 (ja) * | 2003-08-01 | 2010-11-17 | ヤマハ株式会社 | 加速度センサおよびその製造方法 |
JP4499390B2 (ja) * | 2003-09-09 | 2010-07-07 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US7045455B2 (en) * | 2003-10-23 | 2006-05-16 | Chartered Semiconductor Manufacturing Ltd. | Via electromigration improvement by changing the via bottom geometric profile |
US20050112957A1 (en) * | 2003-11-26 | 2005-05-26 | International Business Machines Corporation | Partial inter-locking metal contact structure for semiconductor devices and method of manufacture |
US8432037B2 (en) | 2004-06-10 | 2013-04-30 | Renesas Electronics Corporation | Semiconductor device with a line and method of fabrication thereof |
JP4832807B2 (ja) * | 2004-06-10 | 2011-12-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4786680B2 (ja) * | 2004-06-10 | 2011-10-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR100618343B1 (ko) * | 2004-10-28 | 2006-08-31 | 삼성전자주식회사 | 패키징 기판의 제조방법 및 이를 이용한 패키징 방법. |
US7332428B2 (en) * | 2005-02-28 | 2008-02-19 | Infineon Technologies Ag | Metal interconnect structure and method |
DE102005024914A1 (de) * | 2005-05-31 | 2006-12-07 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Ausbilden elektrisch leitfähiger Leitungen in einem integrierten Schaltkreis |
US7511349B2 (en) * | 2005-08-19 | 2009-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact or via hole structure with enlarged bottom critical dimension |
JP2007109894A (ja) * | 2005-10-13 | 2007-04-26 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP5014632B2 (ja) * | 2006-01-13 | 2012-08-29 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
US7517736B2 (en) * | 2006-02-15 | 2009-04-14 | International Business Machines Corporation | Structure and method of chemically formed anchored metallic vias |
US20070202689A1 (en) * | 2006-02-27 | 2007-08-30 | Samsung Electronics Co., Ltd. | Methods of forming copper vias with argon sputtering etching in dual damascene processes |
DE102006035645B4 (de) * | 2006-07-31 | 2012-03-08 | Advanced Micro Devices, Inc. | Verfahren zum Ausbilden einer elektrisch leitfähigen Leitung in einem integrierten Schaltkreis |
KR100850079B1 (ko) * | 2006-12-26 | 2008-08-04 | 동부일렉트로닉스 주식회사 | 듀얼 다마신 방법을 이용한 금속 배선 형성 방법 |
KR100790452B1 (ko) * | 2006-12-28 | 2008-01-03 | 주식회사 하이닉스반도체 | 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법 |
US7859113B2 (en) * | 2007-02-27 | 2010-12-28 | International Business Machines Corporation | Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method |
US7776737B2 (en) * | 2008-08-14 | 2010-08-17 | International Business Machines Corporation | Reliability of wide interconnects |
US8436252B2 (en) * | 2009-06-30 | 2013-05-07 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
JP5906812B2 (ja) * | 2012-02-29 | 2016-04-20 | 富士通株式会社 | 配線構造、半導体装置及び配線構造の製造方法 |
US8772949B2 (en) | 2012-11-07 | 2014-07-08 | International Business Machines Corporation | Enhanced capture pads for through semiconductor vias |
US9245795B2 (en) * | 2013-05-28 | 2016-01-26 | Intel Corporation | Methods of forming substrate microvias with anchor structures |
TW201532247A (zh) | 2013-10-16 | 2015-08-16 | Conversant Intellectual Property Man Inc | 形成嵌入動態隨機存取記憶體電容器的成本效益佳的方法 |
US9324650B2 (en) | 2014-08-15 | 2016-04-26 | International Business Machines Corporation | Interconnect structures with fully aligned vias |
JP2017069381A (ja) * | 2015-09-30 | 2017-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
CN107564850B (zh) * | 2016-07-01 | 2020-07-07 | 中芯国际集成电路制造(北京)有限公司 | 互连结构及其制造方法 |
US10229826B2 (en) * | 2016-10-21 | 2019-03-12 | Lam Research Corporation | Systems and methods for forming low resistivity metal contacts and interconnects by reducing and removing metallic oxide |
KR102460076B1 (ko) * | 2017-08-01 | 2022-10-28 | 삼성전자주식회사 | 반도체 장치 |
US10475702B2 (en) * | 2018-03-14 | 2019-11-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive feature formation and structure using bottom-up filling deposition |
US10818545B2 (en) * | 2018-06-29 | 2020-10-27 | Sandisk Technologies Llc | Contact via structure including a barrier metal disc for low resistance contact and methods of making the same |
US10964636B2 (en) * | 2018-09-19 | 2021-03-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure with low resistivity and method for forming the same |
US11121025B2 (en) | 2018-09-27 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layer for side wall passivation |
US11177169B2 (en) * | 2019-06-21 | 2021-11-16 | International Business Machines Corporation | Interconnects with gouged vias |
US11183455B2 (en) * | 2020-04-15 | 2021-11-23 | International Business Machines Corporation | Interconnects with enlarged contact area |
US11551967B2 (en) * | 2020-05-19 | 2023-01-10 | Taiwan Semiconductor Manufacturing Company Limited | Via structure and methods for forming the same |
KR20220033289A (ko) | 2020-09-09 | 2022-03-16 | 삼성전자주식회사 | 반도체 패키지 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0262035A (ja) * | 1988-08-29 | 1990-03-01 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置 |
US6040243A (en) * | 1999-09-20 | 2000-03-21 | Chartered Semiconductor Manufacturing Ltd. | Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion |
JP2000208444A (ja) * | 1999-01-14 | 2000-07-28 | Internatl Business Mach Corp <Ibm> | ヴィアめっき方法、ヴィアめっき構造部製造方法、及び多層相互接続構造部 |
US6114243A (en) * | 1999-11-15 | 2000-09-05 | Chartered Semiconductor Manufacturing Ltd | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0799286A (ja) * | 1993-09-29 | 1995-04-11 | Toshiba Corp | 半導体装置 |
US5470790A (en) * | 1994-10-17 | 1995-11-28 | Intel Corporation | Via hole profile and method of fabrication |
KR0138308B1 (ko) * | 1994-12-14 | 1998-06-01 | 김광호 | 층간접촉구조 및 그 방법 |
JP3150095B2 (ja) | 1996-12-12 | 2001-03-26 | 日本電気株式会社 | 多層配線構造の製造方法 |
SG70654A1 (en) | 1997-09-30 | 2000-02-22 | Ibm | Copper stud structure with refractory metal liner |
JP3436672B2 (ja) * | 1997-11-26 | 2003-08-11 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
TW359884B (en) * | 1998-01-07 | 1999-06-01 | Nanya Technology Co Ltd | Multi-level interconnects with I-plug and production process therefor |
US6211085B1 (en) * | 1999-02-18 | 2001-04-03 | Taiwan Semiconductor Company | Method of preparing CU interconnect lines |
US6297155B1 (en) * | 1999-05-03 | 2001-10-02 | Motorola Inc. | Method for forming a copper layer over a semiconductor wafer |
JP2001351977A (ja) * | 2000-04-19 | 2001-12-21 | Internatl Business Mach Corp <Ibm> | バイアスタッドの形成方法および半導体構造 |
US6376353B1 (en) * | 2000-07-03 | 2002-04-23 | Chartered Semiconductor Manufacturing Ltd. | Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects |
US6613664B2 (en) * | 2000-12-28 | 2003-09-02 | Infineon Technologies Ag | Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices |
-
2001
- 2001-02-12 KR KR10-2001-0006812A patent/KR100385227B1/ko active IP Right Grant
- 2001-07-03 TW TW090116243A patent/TW508726B/zh not_active IP Right Cessation
-
2002
- 2002-02-07 US US10/067,342 patent/US6548905B2/en not_active Expired - Lifetime
- 2002-02-12 JP JP2002033534A patent/JP2002246467A/ja active Pending
-
2003
- 2003-01-09 US US10/338,908 patent/US6884710B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0262035A (ja) * | 1988-08-29 | 1990-03-01 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置 |
JP2000208444A (ja) * | 1999-01-14 | 2000-07-28 | Internatl Business Mach Corp <Ibm> | ヴィアめっき方法、ヴィアめっき構造部製造方法、及び多層相互接続構造部 |
US6040243A (en) * | 1999-09-20 | 2000-03-21 | Chartered Semiconductor Manufacturing Ltd. | Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion |
US6114243A (en) * | 1999-11-15 | 2000-09-05 | Chartered Semiconductor Manufacturing Ltd | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7482684B2 (en) | 2005-11-25 | 2009-01-27 | Samsung Electronics Co., Ltd. | Semiconductor device with a dopant region in a lower wire |
US7629239B2 (en) | 2005-11-25 | 2009-12-08 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor device with a dopant region in a lower wire |
Also Published As
Publication number | Publication date |
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US6884710B2 (en) | 2005-04-26 |
US20020109234A1 (en) | 2002-08-15 |
KR20020066567A (ko) | 2002-08-19 |
US20030100181A1 (en) | 2003-05-29 |
JP2002246467A (ja) | 2002-08-30 |
TW508726B (en) | 2002-11-01 |
US6548905B2 (en) | 2003-04-15 |
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