KR100382543B1 - method for forming contact plug of semiconductor device - Google Patents
method for forming contact plug of semiconductor device Download PDFInfo
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- KR100382543B1 KR100382543B1 KR10-2000-0066145A KR20000066145A KR100382543B1 KR 100382543 B1 KR100382543 B1 KR 100382543B1 KR 20000066145 A KR20000066145 A KR 20000066145A KR 100382543 B1 KR100382543 B1 KR 100382543B1
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- tungsten film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Abstract
본 발명은 콘택 플러그용 텅스텐막의 증착 특성을 개선함과 동시에 층간 절연막에서 아웃개싱이 발생하더라도 텅스텐막의 증착 불량을 방지하도록 한 반도체 소자의 콘택 플러그 형성방법에 관한 것으로서, 절연 기판상에 메탈 라인을 형성하는 단계와, 상기 메탈 라인상에 층간 절연막을 형성하는 단계와, 상기 층간 절연막 및 메탈 라인을 선택적으로 제거하여 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 전면에 금속 베리어막을 형성하는 단계와, 상기 금속 베리어막상에 제 1 텅스텐막을 형성하는 단계와, 상기 제 1 텅스텐막상에 콘택 플러그용 제 2 텅스텐막을 30Torr이상의 고압력과 SiH4/WF6을 15 : 30 sccm이상의 고유량으로 형성하는 단계를 포함하여 형성함을 특징으로 한다.The present invention relates to a method for forming a contact plug of a semiconductor device which improves deposition characteristics of a tungsten film for contact plug and prevents deposition of tungsten film even when outgassing occurs in an interlayer insulating film. Forming an interlayer insulating film on the metal line, selectively removing the interlayer insulating film and the metal line to form a contact hole, and forming a metal barrier film on the entire surface including the contact hole; And forming a first tungsten film on the metal barrier film, and forming a second tungsten film for contact plug on the first tungsten film with a high pressure of 30 Torr or more and a high flow rate of SiH 4 / WF 6 of 15:30 sccm or more. It is characterized by including the formation.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 텅스텐(W)막의 증착 불량을 방지하는데 적당한 반도체 소자의 플러그(plug) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a plug of a semiconductor device suitable for preventing deposition failure of a tungsten (W) film.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 콘택 플러그 형성방법을 설명하면 다음과 같다.Hereinafter, a method for forming a contact plug of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래의 반도체 소자의 콘택 플러그 형성방법을 나타낸 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a contact plug of a conventional semiconductor device.
도 1a에 도시한 바와 같이, 절연 기판(도시되지 않음)상에 제 1 티타늄(Ti)막(11)을 형성하고, 상기 제 1 티타늄막(11)상에 알루미늄(Al)막(12), 제 2 티타늄막(13), 제 1 질화 티타늄(TiN)막(14)을 차례로 형성한다.As shown in FIG. 1A, a first titanium (Ti) film 11 is formed on an insulating substrate (not shown), and an aluminum (Al) film 12, The second titanium film 13 and the first titanium nitride (TiN) film 14 are sequentially formed.
여기서 상기 제 1 티타늄막(11), 알루미늄막(12), 제 2 티타늄막(13), 제 1 질화 티타늄막(14)은 메탈 라인(Metal Line)이다.Here, the first titanium film 11, the aluminum film 12, the second titanium film 13, and the first titanium nitride film 14 are metal lines.
도 1b에 도시한 바와 같이, 상기 제 1 질화 티타늄막(14)상에 제 1 TEOS(Tetra Ethyl Ortho Silicate)막(15)을 형성하고, 상기 제 1 TEOS막(15)상에 SOG(Spin On Glass)막(16)을 형성한다.As shown in FIG. 1B, a first TEOS (Tetra Ethyl Ortho Silicate) film 15 is formed on the first titanium nitride film 14, and SOG (Spin On) is formed on the first TEOS film 15. Glass) film 16 is formed.
여기서 상기 SOG막(16)은 TCPS(Tokyoohka Coating Polysilazne Solution)이나 FOx(Fast Oxide)를 사용한다.Here, the SOG film 16 uses Tokyohka Coating Polysilazne Solution (TCPS) or Fast Oxide (FOx).
그리고 상기 SOG막(16)상에 제 2 TEOS막(17)을 형성한다.A second TEOS film 17 is formed on the SOG film 16.
여기서 상기 제 1 TEOS막(15), SOG막(16), 제 2 TEOS막(17)은 메탈 라인간의절연막이다.The first TEOS film 15, the SOG film 16, and the second TEOS film 17 are insulating films between metal lines.
도 1c에 도시한 바와 같이, 포토 및 식각공정을 통해 상기 알루미늄막(12)의 표면이 소정부분 노출되도록 상기 제 2 TEOS막(17), SOG막(16), 제 1 TEOS막(15), 제 1 질화 티타늄막(14), 제 2 티타늄막(13)을 선택적으로 제거하여 콘택홀(18)을 형성한다.As shown in FIG. 1C, the second TEOS layer 17, the SOG layer 16, the first TEOS layer 15, and the second TEOS layer 17 may be exposed to a predetermined portion through the photolithography and etching processes. The contact hole 18 is formed by selectively removing the first titanium nitride film 14 and the second titanium film 13.
도 1d에 도시한 바와 같이, 상기 절연 기판의 전면에 스퍼터 식각(sputter etch)을 통해 콘택홀(18) 형성 후 잔류한 이물질을 제거함과 동시에 콘택홀(18) 상부 부분의 프로파일을 경사지게 식각한다.As illustrated in FIG. 1D, the foreign material remaining after the contact hole 18 is formed through the sputter etching on the entire surface of the insulating substrate and the profile of the upper portion of the contact hole 18 are inclinedly etched.
즉, 상기 콘택홀(18)의 상부 모서리 부분을 스퍼터 에치를 통해 식각한다.That is, the upper edge portion of the contact hole 18 is etched through the sputter etch.
이어, 상기 콘택홀(18)을 포함한 전면에 제 3 티타늄막(19)과 제 2 질화 티타늄막(20)을 차례로 형성한다.Subsequently, a third titanium film 19 and a second titanium nitride film 20 are sequentially formed on the entire surface including the contact hole 18.
여기서 상기 제 3 티타늄막(19)과 제 2 질화 티타늄막(20)은 스퍼터 방식에 의해 형성하므로 콘택홀(18)의 측벽에 증착되는 두께는 다른 부분의 두께보다 얇게 형성된다.In this case, since the third titanium film 19 and the second titanium nitride film 20 are formed by a sputtering method, the thickness deposited on the sidewall of the contact hole 18 is thinner than that of other portions.
한편, 상기 제 3 티타늄막(19)과 제 2 질화 티타늄막(20)은 이후 CVD법에 의한 텅스텐막 증착시 베리어층으로 사용된다.On the other hand, the third titanium film 19 and the second titanium nitride film 20 is used as a barrier layer during the deposition of a tungsten film by the CVD method.
이어, 상기 제 2 질화 티타늄막(20)을 포함한 전면에 WF6와 SiH4의 반응 가스를 이용한 CVD법으로 도 1e에서와 같이, 상기 제 2 질화 티타늄막(20)상에 텅스텐막(21)을 형성한다.Subsequently, a tungsten film 21 is formed on the second titanium nitride film 20 as shown in FIG. 1E by a CVD method using a reaction gas of WF 6 and SiH 4 on the entire surface including the second titanium nitride film 20. To form.
이때 상기 콘택홀(18)의 측면에 노출된 SOG막(16)에서 H2/NH4등의 가스 배출에 의해 상기 텅스텐막(21)의 형성시 반응 가스로 주입되는 WF6, SiH4가스가 아웃개싱(Outgasing)으로 콘택홀(18)의 내부로 들어오는 것을 방해한다.At this time, the WF 6 and SiH 4 gas injected into the reaction gas when the tungsten film 21 is formed by discharging gas such as H 2 / NH 4 from the SOG film 16 exposed on the side surface of the contact hole 18 are formed. Outgassing prevents entry into the contact hole 18.
즉, 상기 텅스텐막(21)이 증착될 때 먼저 텅스텐 핵반응이 일어나게 되는데 이때 콘택홀(18)의 측벽에 노출되어 있는 SOG막(16)으로부터 H2/NH4등이 아웃개싱되기 시작하며 이는 제 2 질화 티타늄막(20)과 제 3 티타늄막(19)의 그레인 바운드리(Grain Boundary)를 통해 나오게 된다.That is, when the tungsten film 21 is deposited, a tungsten nuclear reaction occurs first. At this time, H 2 / NH 4 and the like start outgassing from the SOG film 16 exposed on the sidewall of the contact hole 18. The second titanium nitride layer 20 and the third titanium layer 19 may come out through grain boundaries.
이때 아웃개싱되는 H2/NH4가스는 텅스텐막(21) 형성시 반응 가스로 사용되는 WF6, SiH4가스의 진입을 방해하여 균일한 핵반응이 이루어지지 않게 되고 결과적으로 텅스텐막(21)이 성장할 수 있는 여건이 콘택홀(18) 내부에는 형성되지 않아 필링(filling) 불량을 유발한다.At this time, the outgassed H 2 / NH 4 gas interferes with the entry of WF 6 and SiH 4 gas, which are used as reaction gases when the tungsten film 21 is formed, thereby preventing a uniform nuclear reaction. Conditions that can be grown are not formed inside the contact hole 18, causing a filling failure.
따라서 상기 WF6, SiH4가스들은 H2/NH4기스의 아웃개싱에 의해 방해를 받아 콘택홀(18)의 하부 부분까지 도달하기 힘들뿐 아니라 측벽에서도 아웃개싱에 의하여 핵반응을 일으키지 못하게 되고, 콘택홀(18) 입구에서 반응을 하게 되고 핵반응 이후 텅스텐막(21)의 반응 또한 핵반응이 진행된 부분에서 일어나므로 결과적으로 텅스텐막(21)의 증착이 끝났을 때는 콘택홀(18) 입구 부분이 볼록하게 솟아나게 된다.Accordingly, the WF 6, SiH 4 gas were H 2 / NH 4 and let get disturbed by the outgassing of Kish, as well as difficult to reach the lower part of the contact hole 18 to cause the nuclear reaction by outgassing in the side wall, the contact The reaction of the tungsten film 21 also occurs at the inlet of the hole 18 and the reaction of the tungsten film 21 also occurs after the nuclear reaction. I will.
그러나 상기와 같은 종래의 반도체 소자의 콘택 플러그 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming a contact plug of a semiconductor device has the following problems.
즉, 메탈 라인 사이를 연결하기 위한 콘택을 형성할 때 절연막으로 사용되는 SOG막이 노출되어 고온에서 H2/NH4등의 가스가 배출되고 콘택 플러그 물질인 텅스텐막을 증착할 때 SOG막으로부터 빠져 나오는 가스들이 반응 가스의 콘택홀 진입을 방해하여 텅스텐막의 필링 불량을 유발한다.That is, the SOG film used as the insulating film is exposed when forming a contact for connecting the metal lines so that a gas such as H 2 / NH 4 is discharged at a high temperature and the gas exits from the SOG film when the tungsten film, which is a contact plug material, is deposited. These impede the entry of the reaction gas into the contact hole, causing a poor filling of the tungsten film.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 텅스텐막의 증착 특성을 개선함과 동시에 층간 절연막에서 아웃개싱이 발생하더라도 텅스텐막의 증착 불량을 방지하도록 한 반도체 소자의 콘택 플러그 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method for forming a contact plug of a semiconductor device to improve the deposition characteristics of the tungsten film and to prevent deposition failure of the tungsten film even when outgassing occurs in the interlayer insulating film. Its purpose is to.
도 1a 내지 도 1e는 종래의 반도체 소자의 콘택 플러그 형성방법을 나타낸 공정단면도1A to 1E are cross-sectional views illustrating a method of forming a contact plug in a conventional semiconductor device.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 콘택 플러그 형성방법을 나타낸 공정단면도2A through 2F are cross-sectional views illustrating a method of forming a contact plug in a semiconductor device according to the present invention.
도 3a와 도 3b는 종래와 본 발명에서 콘택 플러그용 텅스텐막 증착상태를 나타낸 맵(Map)3A and 3B are a map showing a deposition state of a tungsten film for a contact plug in the related art and the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
31 : 제 1 티타늄막 32 : 알루미늄막31: first titanium film 32: aluminum film
33 : 제 2 티타늄막 34 : 제 1 질화 티타늄막33: second titanium film 34: first titanium nitride film
35 : 제 1 TEOS막 36 : SOG막35 first TEOS film 36 SOG film
37 : 제 2 TEOS막 38 : 콘택홀37: second TEOS film 38: contact hole
39 : 제 3 티타늄막 40 : 제 2 질화 티타늄막39: third titanium film 40: second titanium nitride film
41 : 제 1 텅스텐막 42 : 제 2 텅스텐막41: first tungsten film 42: second tungsten film
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 콘택 플러그 형성방법은 절연 기판상에 메탈 라인을 형성하는 단계와, 상기 메탈 라인상에 층간 절연막을 형성하는 단계와, 상기 층간 절연막 및 메탈 라인을 선택적으로 제거하여 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 전면에 금속 베리어막을 형성하는 단계와, 상기 금속 베리어막상에 제 1 텅스텐막을 형성하는 단계와, 상기 제 1 텅스텐막상에 콘택 플러그용 제 2 텅스텐막을 30Torr이상의 고압력과 SiH4/WF6을 15 : 30 sccm이상의 고유량으로 형성하는 단계를 포함하여 형성함을 특징으로 한다.The method of forming a contact plug of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a metal line on an insulating substrate, forming an interlayer insulating film on the metal line, the interlayer insulating film and metal Selectively removing lines to form contact holes, forming a metal barrier film on the entire surface including the contact holes, forming a first tungsten film on the metal barrier film, and forming a contact on the first tungsten film. And forming a second tungsten film for the plug at a high pressure of 30 Torr or more and SiH 4 / WF 6 at a high flow rate of 15:30 sccm or more.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 콘택 플러그형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method for forming a contact plug of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 콘택 플러그 형성방법을 나타낸 공정단면도이다.2A to 2F are process cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 절연 기판(도시되지 않음)상에 제 1 티타늄(Ti)막(31)을 형성하고, 상기 제 1 티타늄막(31)상에 알루미늄(Al)막(32), 제 2 티타늄막(33), 제 1 질화 티타늄(TiN)막(34)을 차례로 형성한다.As shown in FIG. 2A, a first titanium (Ti) film 31 is formed on an insulating substrate (not shown), and an aluminum (Al) film 32, on the first titanium film 31, The second titanium film 33 and the first titanium nitride (TiN) film 34 are sequentially formed.
여기서 상기 제 1 티타늄막(31), 알루미늄막(32), 제 2 티타늄막(33), 제 1 질화 티타늄막(34)은 메탈 라인(Metal Line)이다.The first titanium film 31, the aluminum film 32, the second titanium film 33, and the first titanium nitride film 34 are metal lines.
도 2b에 도시한 바와 같이, 상기 제 1 질화 티타늄막(34)상에 제 1 TEOS(Tetra Ethyl Ortho Silicate)막(35)을 형성하고, 상기 제 1 TEOS막(35)상에 SOG(Spin On Glass)막(36)을 형성한다.As shown in FIG. 2B, a first TEOS (Tetra Ethyl Ortho Silicate) film 35 is formed on the first titanium nitride film 34, and a SOG (Spin On) is formed on the first TEOS film 35. Glass) film 36 is formed.
여기서 상기 SOG막(36)은 TCPS(Tokyoohka Coating Polysilazne Solution)이나 FOx(Fast Oxide)를 사용한다.Here, the SOG film 36 uses Tokyohka Coating Polysilazne Solution (TCPS) or Fast Oxide (FOx).
그리고 상기 SOG막(36)상에 제 2 TEOS막(37)을 형성한다.A second TEOS film 37 is formed on the SOG film 36.
여기서 상기 제 1 TEOS막(35), SOG막(36), 제 2 TEOS막(37)은 메탈 라인 사이의 절연막이다.The first TEOS film 35, the SOG film 36, and the second TEOS film 37 are insulating films between metal lines.
도 2c에 도시한 바와 같이, 포토 및 식각공정을 통해 상기 알루미늄막(32)의 표면이 소정부분 노출되도록 상기 제 2 TEOS막(37), SOG막(36), 제 1 TEOS막(35), 제 1 질화 티타늄막(34), 제 2 티타늄막(33)을 선택적으로 제거하여 콘택홀(38)을 형성한다.As shown in FIG. 2C, the second TEOS film 37, the SOG film 36, the first TEOS film 35, and the like are exposed to a predetermined portion of the surface of the aluminum film 32 through a photo and etching process. The first titanium nitride film 34 and the second titanium film 33 are selectively removed to form a contact hole 38.
도 2d에 도시한 바와 같이, 상기 절연 기판의 전면에 스퍼터 에치(sputter etch)를 통해 콘택홀(38) 형성 후 잔류한 이물질을 제거함과 동시에 콘택홀(38) 상부 부분의 프로파일을 경사지게 식각한다.As illustrated in FIG. 2D, the foreign material remaining after the contact hole 38 is formed through the sputter etch on the entire surface of the insulating substrate is removed, and the profile of the upper portion of the contact hole 38 is etched obliquely.
즉, 상기 콘택홀(38)의 상부 모서리 부분을 스퍼터 에치를 통해 식각한다.That is, the upper edge portion of the contact hole 38 is etched through the sputter etch.
이어, 상기 콘택홀(38)을 포함한 전면에 스퍼터 증착으로 제 3 티타늄막(39)과 제 2 질화 티타늄막(40)을 차례로 형성한다.Subsequently, a third titanium film 39 and a second titanium nitride film 40 are sequentially formed by sputter deposition on the entire surface including the contact hole 38.
도 2e에 도시한 바와 같이, 상기 제 2 질화 티타늄막(40)상에 스퍼터 증착에 의해 제 1 텅스텐막(41)을 형성한다.As shown in Fig. 2E, a first tungsten film 41 is formed on the second titanium nitride film 40 by sputter deposition.
여기서 상기 스퍼터 증착에 의해 형성된 제 1 텅스텐막(41)은 이후 CVD 텅스텐막 형성시 베리어 물질로 작용함과 동시에 텅스텐(W)의 핵반응시 시드층(Seed Layer)으로 작용한다.Here, the first tungsten film 41 formed by the sputter deposition serves as a barrier material when forming a CVD tungsten film and also serves as a seed layer during nuclear reaction of tungsten (W).
도 2f에 도시한 바와 같이, 상기 제 1 텅스텐막(41)상에 WF6와 SiH4의 반응 가스를 이용한 CVD법에 의해 제 2 텅스텐막(42)을 형성한다.As shown in Fig. 2F, a second tungsten film 42 is formed on the first tungsten film 41 by a CVD method using a reaction gas of WF 6 and SiH 4 .
이때 상기 제 2 텅스텐막(42)은 핵반응이 빨리 일어날 수 있도록 고압/고유량의 공정 조건을 유지하면서 형성한다.In this case, the second tungsten film 42 is formed while maintaining high pressure / high flow process conditions so that a nuclear reaction can occur quickly.
즉, 압력을 30Torr 이상으로 하고, 반응 가스 유량을 SiH4/WF6를 15 : 30 sccm이상으로 하고, 상기 반응 가스에 H2를 500sccm이상 첨가한다.That is, the pressure is set to 30 Torr or more, the reaction gas flow rate is set to SiH 4 / WF 6 of 15:30 sccm or more, and H 2 is added to the reaction gas of 500 sccm or more.
여기서 상기 CVD법에 의한 제 2 텡스텐막(42)의 핵반응이 일어나기 전에 465℃이상의 온도를 상승 및 유지하여 아웃개싱을 미리 발생하게 하거나 핵반응의 온도를 370℃이하로 낮추어 아웃개싱을 줄일 수도 있다.Here, before the nuclear reaction of the second tungsten film 42 by the CVD method occurs, the temperature of 465 ° C. or higher may be raised and maintained to cause outgassing in advance, or the temperature of the nuclear reaction may be reduced to 370 ° C. or lower to reduce the outgassing. .
일반적으로 텅스텐(W)의 반응은 온도가 증가할수록 활발해지고 또한 압력이 증가할수록 활발해진다. 현재 CVD 텅스텐의 증착은 400℃ 부근에서 진행되고 있으며 먼저 핵반응이 진행된 후 텅스텐막의 증착이 진행되게 된다.In general, the reaction of tungsten (W) becomes active as the temperature increases and also becomes active as the pressure increases. Currently, the deposition of CVD tungsten is performed in the vicinity of 400 ° C., and the deposition of tungsten film proceeds first after the nuclear reaction proceeds.
또한, 종래 기술보다 압력 증가로 인하여 반응 가스들이 콘택홀(38)의 내부 진입이 용이해지며 또한 반응성이 우수하므로 동일 두께를 형성하는데 1/4정도의 시간밖에 걸리지 않는다.In addition, due to the increase in pressure than the prior art, the reaction gases are easier to enter the contact hole 38 and excellent in reactivity, so that it takes only 1/4 time to form the same thickness.
그러므로 SOG(36)에서 아웃개싱이 발생하는 시간을 감소시키는 역할을 할 수 있다. 더구나 베리어 물질로 스퍼터 증착에 의해 제 1 텅스텐막(41)을 증착하게 되면 자체로서 SOG막(36)의 아웃개싱을 억제할 수 있을 뿐 아니라 제 2 텅스텐막(42)의 핵반응시 시드층(Seed Layer)으로 작용하기 때문에 텅스텐(W) 핵반응 시간은 더욱더 짧아지게 된다.Therefore, it may serve to reduce the time that outgassing occurs in the SOG 36. In addition, if the first tungsten film 41 is deposited by barrier material, the outgassing of the SOG film 36 may be suppressed by itself, and the seed layer may be seeded during the nuclear reaction of the second tungsten film 42. Tungsten (W) nuclear reaction time becomes shorter because it acts as a layer.
도 3a와 도 3b는 종래와 본 발명에서 콘택 플러그용 텅스텐막 증착상태를 나타낸 맵(Map)이다.3A and 3B are maps showing a deposition state of a tungsten film for a contact plug in the related art and the present invention.
즉, 콘택 플러그용 텅스텐막의 증착이 완료된 후에 이물 검사를 실시헤 보면 종래의 기술을 사용한 경우는 도 3a와 같이 SOG막의 아웃개싱에 의한 불량이 집단적으로 발생함을 볼 수 있으며, 본 발명의 고압/고유량의 공정 조건을 사용한 경우에는 도 3와 같이 불량이 발생되지 않음을 알 수 있다.That is, when the foreign material inspection is performed after the deposition of the contact plug tungsten film is completed, it can be seen that when the conventional technique is used, defects due to outgassing of the SOG film are collectively generated as shown in FIG. 3A. In the case of using the high-flow process conditions, it can be seen that no defect occurs as shown in FIG. 3.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 콘택 플러그 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming a contact plug of a semiconductor device according to the present invention has the following effects.
첫째, CVD 텅스텐막의 시드층으로 스퍼터 증착에 의해 텅스텐막을 형성함으로서 CVD 텅스텐의 핵반응 시간을 단축할 수 있어 SOG막의 아웃개싱이 발생하는 시간을 줄일 수 있다.First, by forming a tungsten film by sputter deposition as a seed layer of the CVD tungsten film, it is possible to shorten the nuclear reaction time of the CVD tungsten, thereby reducing the time for outgassing of the SOG film.
둘째, 고압/고유량으로 CVD 텅스텐막을 증착함으로서 반응 가스들의 홀 내부 진입이 용이해지고 반응성이 우수하여 동일한 두께의 텅스텐막을 형성할 때 종래보다 4배 이상 빠르게 형성할 수 있어 아웃개싱이 발생하는 시간을 줄일 수 있다.Second, by depositing the CVD tungsten film at high pressure / high flow rate, it is easy to enter the inside of the hole of the reaction gases and the reactivity is excellent, so that when forming the tungsten film of the same thickness, it can be formed more than four times faster than the conventional ones. Can be reduced.
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| KR200453852Y1 (en) * | 2008-09-30 | 2011-05-30 | 주식회사 진성테크 | Clamp cover |
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