KR100367487B1 - 반도체소자의 제조방법 - Google Patents
반도체소자의 제조방법 Download PDFInfo
- Publication number
- KR100367487B1 KR100367487B1 KR10-2000-0083804A KR20000083804A KR100367487B1 KR 100367487 B1 KR100367487 B1 KR 100367487B1 KR 20000083804 A KR20000083804 A KR 20000083804A KR 100367487 B1 KR100367487 B1 KR 100367487B1
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- South Korea
- Prior art keywords
- film
- forming
- alloy layer
- diffusion barrier
- metal wiring
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (5)
- 소정의 하부구조물이 구비되는 반도체기판 상부에 제1층간절연막을 형성하는 공정과,상기 제1층간절연막 상부에 제1금속배선을 형성하는 공정과,전체표면 상부에 비아콘택홀과 제2금속배선으로 예정되는 트랜치가 구비되는 제2층간절연막을 형성하는 공정과,전체표면 상부에 소정 두께의 제1확산방지막을 형성하는 공정과,상기 제1확산방지막 상부에 제1Cu/Cr 합금층을 소정 두께 형성하는 공정과,상기 제1Cu/Cr 합금층 상부에 Cu막을 형성하여 상기 트랜치 및 비아콘택홀을 매립하는 공정과,상기 Cu막, 제1Cu/Cr 합금층 및 제1확산방지막을 화학적 기계적 연마공정으로 평탄화시켜 상기 비아콘택홀과 트랜치에 매립되는 제2금속배선을 형성하는 공정과,상기 제2금속배선 상부에 제2Cu/Cr합금층을 형성하는 공정과,전체표면 상부에 제2확산방지막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 제1확산방지막은 Ta막, TaN막 및 TiN막으로 이루어지는 군에서 선택되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 제1Cu/Cr 합금층은 물리기상증착방법, 화학기상증착방법 또는 코-스퍼터링(co-sputtering)방법으로 형성되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 제2Cu/Cr 합금층은 전체표면 상부에 물리기상증착방법, 화학기상증착방법 또는 코-스퍼터링(co-sputtering)방법으로 형성한 다음, 사진식각공정에 의해 상기 제2금속배선 표면에 형성되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 제2Cu/Cr 합금층은 전기도금 (electroplating)방법으로 형성하여 상기 제2금속배선 표면에만 형성되는 것을 특징으로 하는 반도체소자의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0083804A KR100367487B1 (ko) | 2000-12-28 | 2000-12-28 | 반도체소자의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0083804A KR100367487B1 (ko) | 2000-12-28 | 2000-12-28 | 반도체소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020054641A KR20020054641A (ko) | 2002-07-08 |
KR100367487B1 true KR100367487B1 (ko) | 2003-01-10 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR10-2000-0083804A KR100367487B1 (ko) | 2000-12-28 | 2000-12-28 | 반도체소자의 제조방법 |
Country Status (1)
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KR (1) | KR100367487B1 (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100906307B1 (ko) * | 2002-11-21 | 2009-07-07 | 매그나칩 반도체 유한회사 | 반도체 소자의 제조 방법 |
KR100720530B1 (ko) * | 2005-12-29 | 2007-05-22 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속배선 및 그의 형성방법 |
US20130240484A1 (en) * | 2012-03-19 | 2013-09-19 | Lam Research Corporation | Electroless copper alloy capping |
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2000
- 2000-12-28 KR KR10-2000-0083804A patent/KR100367487B1/ko active IP Right Grant
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KR20020054641A (ko) | 2002-07-08 |
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