KR100362703B1 - 박막트랜지스터 제조방법 - Google Patents
박막트랜지스터 제조방법 Download PDFInfo
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- KR100362703B1 KR100362703B1 KR1019990049938A KR19990049938A KR100362703B1 KR 100362703 B1 KR100362703 B1 KR 100362703B1 KR 1019990049938 A KR1019990049938 A KR 1019990049938A KR 19990049938 A KR19990049938 A KR 19990049938A KR 100362703 B1 KR100362703 B1 KR 100362703B1
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- 238000000034 method Methods 0.000 title claims description 55
- 238000005468 ion implantation Methods 0.000 claims abstract description 67
- 239000004020 conductor Substances 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000010408 film Substances 0.000 claims description 33
- 239000010409 thin film Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 13
- 239000011521 glass Substances 0.000 claims description 6
- 239000004973 liquid crystal related substance Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims 2
- 238000010030 laminating Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 239000002245 particle Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 31
- 239000004065 semiconductor Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000005401 electroluminescence Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000615 nonconductor Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Liquid Crystal (AREA)
Abstract
Description
Claims (14)
- 박막트랜지스터의 제조방법에 있어서,기판 상에 게이트 절연막 및 게이트막을 형성하는 단계;상기 게이트막을 패터닝하여 전기적으로 고립된 복수의 게이트 패턴 및 상기 게이트 패턴 사이에 상기 게이트 패턴의 상호간을 연결하는 보조 도체 패턴을 형성하는 단계;상기 게이트 패턴을 이온주입 마스크로 이용하여 불순물 이온주입을 실시하여 소오스 및 드레인 영역을 형성하는 단계; 및상기 보조 도체 패턴을 제거하는 단계를 구비하는 박막트랜지스터 제조방법.
- 제 1 항에 있어서,상기 박막트랜지스터는 표시장치를 위한 것임을 특징으로 하는 박막트랜지스터 제조방법.
- 제 2 항에 있어서,상기 도체 패턴은 금속 재질로 형성하는 것을 특징으로 하는 위한 박막트랜지스터 제조방법.
- 삭제
- 제 4 항에 있어서,상기 이온주입은 폴리실리콘형 액정표시장치의 P채널 트랜지스터의 소오스/드레인 영역을 형성하기 위한 이온주입인 것을 특징으로 하는 박막트랜지스터 제조방법.
- 제 2 항에 있어서,상기 보조 도체 패턴은 기판에 넓은 영역에 걸쳐 형성되는 큰 게이트 패턴과 좁은 영역에 국한되는 작은 게이트 패턴 사이 간격이 좁은 부분이 있는 경우에 상기 큰 게이트 패턴과 작은 게이트 패턴 사이에서만 형성되는 것을 특징으로 하는 박막트랜지스터 제조방법.
- 제 6 항에 있어서,상기 보조 도체 패턴은 상기 사이 간격이 좁은 부분을 얇은 절연막에 의해 매몰된 채로 가로지르는 도전성 물질이 있을 때 형성되는 것을 특징으로 하는 박막트랜지스터 제조방법.
- 제 2 항에 있어서,상기 이온주입이 이루어지는 단계는 복수 회 존재하고 상기 보조 도체 패턴은 상기 이온주입이 이루어지는 단계 가운데 특정 이온주입 단계에 대해서만 형성되는 것을 특징으로 하는 박막트랜지스터 제조방법.
- 제 2 항에 있어서,상기 보조 도체 패턴을 포함하여 상기 게이트 패턴 전체가 동시에 형성되는 것을 특징으로 하는 박막트랜지스터 제조방법.
- P채널 트랜지스터와 N채널 트랜지스터를 함께 구비하여 사용하는 폴리실리콘형 박막트랜지스터 액정표시장치의 박막트랜지스터 제조방법에 있어서,글래스 기판에 폴리실리콘층을 적층하고 액티브 영역에만 남기는 패터닝 작업을 하는 단계,게이트 절연막과 게이트막을 적층하는 단계,상기 게이트막을 패터닝 작업을 통해 P 또는 N채널 트랜지스터 영역의 게이트막은 보존하고 다른 채널의 트랜지스터 영역의 게이트막으로 게이트 패턴을 형성하며 모든 잔류 게이트막이 연결되도록 보조 게이트 패턴을 형성하는 단계,상기 잔류 게이트막을 이온주입 마스크로 N 또는 P형 불순물 이온주입을 실시하는 단계,상기 잔류 게이트막 위로 도체 게이트 보조막을 적층하고 패터닝 작업을 통해 N 또는 P채널 트랜지스터 영역에는 상기 게이트 패턴과 상기 액티브 영역을 보호하도록 게이트 보조막을 보존하고 다른 채널 트랜지스터 영역에는 게이트 보조막으로 게이트 가패턴을 형성하며 모든 잔류 게이트 보조막이 연결되도록 보조 게이트 가패턴을 형성하는 단계,상기 잔류 게이트 보조막을 식각 마스크로 게이트막을 식각하여 P 또는 N채널 트랜지스터 영역의 게이트 패턴을 형성하고 상기 보조 게이트 패턴을 제거하는 단계,상기 잔류 게이트 보조막을 이온주입 마스크로 P 또는 N형 불순물 이온주입을 실시하는 단계 및상기 잔류 게이트 보조막을 식각으로 제거하는 단계를 구비하여 이루어지는 것을 특징으로 하는 박막트랜지스터 제조방법.
- 제 10 항에 있어서,P채널 트랜지스터 구조가 먼저 형성되며,상기 N채널 트랜지스터 영역에서 상기 잔류 게이트 보조막을 식각 마스크로 게이트막을 식각할 때 상기 게이트 보조막과 상기 게이트막에 대해 식각선택비가 큰 식각물질을 사용하여 등방성 식각을 하여 상기 N채널 트랜지스터 영역의 게이트 패턴의 폭이 상기 게이트 가패턴의 폭보다 일정 간격 좁게 형성하는 것을 특징으로 하는 박막트랜지스터 제조방법.
- 제 11 항에 있어서,상기 잔류 게이트 보조막을 제거하는 단계 후에 N형 불순물을 저농도로 도핑하여 상기 N채널 트랜지스터에서 LDD(Lightly Doped Drain) 구조를 형성하는 것을 특징으로 하는 박막트랜지스터 제조방법.
- 제 11 항에 있어서,상기 게이트막은 알미늄을 함유하는 금속재질로 형성하며, 상기 게이트 보조막은 크롬으로 형성하는 것을 특징으로 하는 박막트랜지스터 제조방법.
- 제 10 항에 있어서,N채널 트랜지스터 구조가 먼저 형성되는 것을 특징으로 하는 박막트랜지스터 제조방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990049938A KR100362703B1 (ko) | 1999-11-11 | 1999-11-11 | 박막트랜지스터 제조방법 |
JP2000343935A JP4566388B2 (ja) | 1999-11-11 | 2000-11-10 | 薄膜トランジスタ製造方法 |
US09/709,648 US6340609B1 (en) | 1999-11-11 | 2000-11-13 | Method of forming thin film transistor |
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KR1019990049938A KR100362703B1 (ko) | 1999-11-11 | 1999-11-11 | 박막트랜지스터 제조방법 |
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KR20010046242A KR20010046242A (ko) | 2001-06-05 |
KR100362703B1 true KR100362703B1 (ko) | 2002-11-29 |
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US (1) | US6340609B1 (ko) |
JP (1) | JP4566388B2 (ko) |
KR (1) | KR100362703B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100900543B1 (ko) * | 2002-11-14 | 2009-06-02 | 삼성전자주식회사 | 박막 트랜지스터 기판의 다결정 규소 박막 트랜지스터 및그의 형성 방법 |
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US6140160A (en) * | 1997-07-28 | 2000-10-31 | Micron Technology, Inc. | Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure |
GB2398975B (en) * | 2001-02-01 | 2005-02-23 | Fujitsu Ltd | Communications systems |
KR100719933B1 (ko) * | 2006-04-06 | 2007-05-18 | 비오이 하이디스 테크놀로지 주식회사 | 다결정 실리콘 채널을 갖는 박막 트랜지스터의 제조방법 |
US8153513B2 (en) * | 2006-07-25 | 2012-04-10 | Silicon Genesis Corporation | Method and system for continuous large-area scanning implantation process |
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JPS6265455A (ja) * | 1985-09-18 | 1987-03-24 | Toshiba Corp | 表示装置 |
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JPH0555258A (ja) * | 1991-08-29 | 1993-03-05 | Sharp Corp | 薄膜トランジスタの製造方法 |
JP2809247B2 (ja) * | 1992-02-12 | 1998-10-08 | シャープ株式会社 | 薄膜半導体素子の製造方法 |
JP3257086B2 (ja) * | 1992-11-12 | 2002-02-18 | セイコーエプソン株式会社 | 相補性薄膜半導体装置の製造方法 |
EP0663697A4 (en) * | 1993-07-26 | 1997-11-26 | Seiko Epson Corp | THIN FILM SEMICONDUCTOR DEVICE, ITS MANUFACTURE AND ITS DISPLAY SYSTEM. |
JP3139896B2 (ja) * | 1993-11-05 | 2001-03-05 | 株式会社東芝 | 半導体レイアウト方法 |
JP3578424B2 (ja) * | 1995-09-13 | 2004-10-20 | シャープ株式会社 | アクティブマトリクス基板の製造方法 |
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JPH1197705A (ja) * | 1997-09-23 | 1999-04-09 | Semiconductor Energy Lab Co Ltd | 半導体集積回路 |
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1999
- 1999-11-11 KR KR1019990049938A patent/KR100362703B1/ko active IP Right Grant
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2000
- 2000-11-10 JP JP2000343935A patent/JP4566388B2/ja not_active Expired - Lifetime
- 2000-11-13 US US09/709,648 patent/US6340609B1/en not_active Expired - Lifetime
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JPS6265455A (ja) * | 1985-09-18 | 1987-03-24 | Toshiba Corp | 表示装置 |
Cited By (1)
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KR100900543B1 (ko) * | 2002-11-14 | 2009-06-02 | 삼성전자주식회사 | 박막 트랜지스터 기판의 다결정 규소 박막 트랜지스터 및그의 형성 방법 |
Also Published As
Publication number | Publication date |
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KR20010046242A (ko) | 2001-06-05 |
US6340609B1 (en) | 2002-01-22 |
JP4566388B2 (ja) | 2010-10-20 |
JP2001177107A (ja) | 2001-06-29 |
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