KR100358128B1 - Method for forming gate electrode - Google Patents
Method for forming gate electrode Download PDFInfo
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- KR100358128B1 KR100358128B1 KR1019950008099A KR19950008099A KR100358128B1 KR 100358128 B1 KR100358128 B1 KR 100358128B1 KR 1019950008099 A KR1019950008099 A KR 1019950008099A KR 19950008099 A KR19950008099 A KR 19950008099A KR 100358128 B1 KR100358128 B1 KR 100358128B1
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- South Korea
- Prior art keywords
- gate electrode
- film
- layer
- oxide film
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 229910007991 Si-N Inorganic materials 0.000 claims description 2
- 229910006294 Si—N Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 8
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 8
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052731 fluorine Inorganic materials 0.000 abstract description 3
- 239000011737 fluorine Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 제조 공정중 게이트 전극 형성 방법에 관한 것으로, 특히 폴리실리콘막 및 실리사이드막이 적층된 구조를 갖는 폴리사이드 구조의 게이트 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode during a semiconductor manufacturing process, and more particularly to a method of forming a gate electrode having a polyside structure having a structure in which a polysilicon film and a silicide film are laminated.
일반적으로, 게이트 전극은 폴리실리콘막을 사용하는데, 게이트 전극의 저항값을 낮추기 위하여 폴리실리콘막 상에 비저항값이 낮은 실리사이드막을 형성한 폴리사이드 구조의 게이트 전극을 사용하고 있다.Generally, a polysilicon film is used as the gate electrode, and a gate electrode having a polyside structure in which a silicide film having a low specific resistance is formed on the polysilicon film is used to reduce the resistance of the gate electrode.
제 1 도는 종래의 폴리사이드 구조를 갖는 게이트 전극의 단면도로서, 도면애 도시된 바와 같이 필드산화막(12)이 형성된 반도체 기판(11)상의 게이트 산화막(13) 상부에 폴리실리콘막(14) 및 텅스텐 실리사이드막(15)으로 이루어지는 게이트전극이 형성되어 있다.1 is a cross-sectional view of a gate electrode having a conventional polyside structure, as shown in the drawing. A gate electrode made of the silicide film 15 is formed.
여기서, 텅스텐실리사이드막(15)은 폴리실리콘막 상에 증착시 아래와 같은 반응식1에 의해 증착된다.Here, the tungsten silicide film 15 is deposited by the following Scheme 1 when deposited on the polysilicon film.
7SiH2Cl2+ 2WF6→ 2WSi2+ 3SiF4+ 14H2......................<반응식1>7SiH 2 Cl 2 + 2WF 6 → 2WSi 2 + 3SiF 4 + 14H 2 ...... <Scheme 1>
이때, 플로린(F, fluorine) 생성되어, F가 폴리실리콘막을 뚫고 게이트 산화막으로 침투하게 된다.At this time, fluorine (F, fluorine) is generated, so that F penetrates the polysilicon film and penetrates into the gate oxide film.
결국, 게이트 산화막으로 침투된 F는 게이트 산화막(SiO2)과 실리콘기판 계면의 Si-O2결합을 끊어버리면서 게이트 산화막의 두께를 증가시키게 되고, 또한 게이트 산화막으로 침투된 F의 일부는 트랩으로 작용함으로써 게이트 전극의 스트레스시 브레이크다운(Breakdown)의 원인이 되어 소자의 특성을 저하시키는 문제점이 있었다.As a result, F penetrated into the gate oxide film increases the thickness of the gate oxide film by breaking the Si-O 2 bond between the gate oxide film (SiO 2 ) and the silicon substrate interface, and part of F penetrated into the gate oxide film is trapped. This acts as a cause of breakdown during stress of the gate electrode, thereby degrading the characteristics of the device.
따라서, 본 발명은 F가 게이트 산화막으로 침투되는 것을 방지하여 소자특성을 개선하는데 적합한 폴리사이드 구조의 게이트 전극 형성 방법을 제공함을 그 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a gate electrode having a polyside structure suitable for preventing F from penetrating into the gate oxide film and improving device characteristics.
상기 목적을 달성하기 위하여 본 발명은 폴리사이드 구조의 게이트 전극 형성 방법에 있어서, 게이트 산화막 상에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상부 표면을 산화시켜 산화막을 형성하는 단계; 상기 산화막을 질소 댕글링 본드(Si-N) 구조로 변형시키는 단계; 및 결과물 전면에 실리사이드막을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a gate electrode having a polyside structure, comprising: forming a polysilicon film on a gate oxide film; Oxidizing an upper surface of the polysilicon film to form an oxide film; Transforming the oxide layer into a nitrogen dangling bond (Si-N) structure; And forming a silicide film on the entire surface of the resultant.
이하, 첨부된 도면 제 2A 도 내지 제 2C 도를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the attached drawings 2A to 2C.
먼저, 제 2A 도에 도시된 바와 같이 실리콘 기판(21) 상의 게이트 산화막(22) 상부에 폴리실리콘막(23)을 1500~2000Å 형성한 상태에서, 850℃의 온도, O2/H2= 8/l0의 공정가스, 15분 정도의 시간을 공정조건으로 산화공정을 진행하여 폴리실리콘막 상에 15~20Å의 산화막(24)을 형성한다.First, as shown in FIG. 2A, a polysilicon film 23 is formed on the silicon oxide film 21 on the gate oxide film 22 at a temperature of 850 ° C., O 2 / H 2 = 8 The oxidation process is carried out under a process gas of / 10 and a time of about 15 minutes to form an oxide film 24 of 15 to 20 kPa on the polysilicon film.
이어서, 제 2B 도에 도시된 바와 같이 상기 산화 공정이 진행된 공정튜브에서 계속적으로(In-Situ) NH3가스를 사용하여 950℃의 온도에서 30분 정도 열처리하여 상기 산화막(24)을 Si-N 결합 구조의 질소 댕글링 본드막(24')으로 변화시킨다.Subsequently, as illustrated in FIG. 2B, the oxide film 24 is heat-treated at a temperature of 950 ° C. for 30 minutes using NH 3 gas (In-Situ). It changes to the nitrogen dangling bond film 24 'of a bonding structure.
제 2C 도는 상기 질소 댕글링 본드막(24')상에 텅스텐 실리사이드막(25)을 형성하고, 게이트 마스크를 사용하여 패터닝한 상태로서, 텅스텐 실리사이드막(25)형성시 생성된 플로린(F)은 질소 댕글링 본드막(24')을 뚫지 못하고 이후의 후속공정을 거치면서 밖으로 확산되어 소멸되게 된다.2C or tungsten silicide film 25 is formed on the nitrogen dangling bond film 24 'and patterned using a gate mask. Florin F generated when the tungsten silicide film 25 is formed The nitrogen dangling bond layer 24 ′ cannot be penetrated and then diffuses out and disappears through the subsequent process.
참고적으로, 질소 댕글링 본드막의 결합 에너지는 4.5eV 로서 F에 의하여 그 결합에너지는 깨지지 않는다.For reference, the binding energy of the nitrogen dangling bond film is 4.5 eV, and the binding energy is not broken by F.
이상, 상기 설명과 같이 이루어지는 본 발명은 폴리사이드 게이트 전극 구조를 이루는 텅스텐 실리사이드막 형성시 발생한 플로린이 게이트 산화막으로 침투하는 것을 방지하며, 또한 질소 댕글링 본드막이 텅스텐 실리사이드막의 스트레스를 완화하여 소자의 특성을 향상시키는 효과가 있다.As described above, the present invention as described above prevents invasion of the florin generated during the formation of the tungsten silicide film forming the polyside gate electrode structure into the gate oxide film, and the nitrogen dangling bond film relieves the stress of the tungsten silicide film to provide characteristics of the device. Has the effect of improving.
재 1 도는 종래의 폴리사이드 구조를 갖는 게이트 전극 단면도.1 is a cross-sectional view of a gate electrode having a conventional polyside structure.
제 2A 도 내지 제 2C 도는 본 발명에 따른 폴리사이드 구조를 갖는 게이트전극 단면도.2A through 2C are cross-sectional views of a gate electrode having a polyside structure according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘 기판 22 : 게이트 산화막21 silicon substrate 22 gate oxide film
23 : 폴리실리콘막 24 : 산화막23 polysilicon film 24 oxide film
24' : 질소 댕글링 본드막 25 : 텅스텐 실리사이드막24 ': nitrogen dangling bond film 25: tungsten silicide film
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950008099A KR100358128B1 (en) | 1995-04-07 | 1995-04-07 | Method for forming gate electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950008099A KR100358128B1 (en) | 1995-04-07 | 1995-04-07 | Method for forming gate electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960039141A KR960039141A (en) | 1996-11-21 |
| KR100358128B1 true KR100358128B1 (en) | 2003-01-14 |
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ID=37490384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950008099A KR100358128B1 (en) | 1995-04-07 | 1995-04-07 | Method for forming gate electrode |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100358128B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100402105B1 (en) * | 1996-12-28 | 2004-02-14 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100505449B1 (en) * | 1998-12-24 | 2005-10-14 | 주식회사 하이닉스반도체 | Method of forming polyside gate electrode of semiconductor device |
-
1995
- 1995-04-07 KR KR1019950008099A patent/KR100358128B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100402105B1 (en) * | 1996-12-28 | 2004-02-14 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR100505449B1 (en) * | 1998-12-24 | 2005-10-14 | 주식회사 하이닉스반도체 | Method of forming polyside gate electrode of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960039141A (en) | 1996-11-21 |
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