KR100357303B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR100357303B1 KR100357303B1 KR1019990063490A KR19990063490A KR100357303B1 KR 100357303 B1 KR100357303 B1 KR 100357303B1 KR 1019990063490 A KR1019990063490 A KR 1019990063490A KR 19990063490 A KR19990063490 A KR 19990063490A KR 100357303 B1 KR100357303 B1 KR 100357303B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- insulating film
- film
- device isolation
- forming
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 고집적소자의 트랜지스터 제조공정시 트렌치를 이용하여 소자분리영역을 정의하는 공정을 실시할 때 게이트전극으로 예정되는 부분도 동시에 정의하고, 게이트전극이 형성될 부분에 형성되는 절연막을 제거한 다음 게이트전극을 형성하여 게이트전극 하부에 형성되는 채널길이(channel length)의 증가로 인하여 문턱전압(threshold voltage)을 감소시킬 수 있으므로 저전압에서도 동작가능한 트랜지스터를 제조함으로써 소자의 고집적화 및 고속화를 유리하게 하는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, and when defining a device isolation region by using a trench during a transistor manufacturing process of a high-integration device, a portion defined as a gate electrode is simultaneously defined and a gate electrode is formed. Since the threshold voltage can be reduced by increasing the channel length formed under the gate electrode by removing the insulating film formed in the portion, the transistor can be operated at low voltage. It is a technology that favors high integration and high speed.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 고집적 소자의 제조공정시 트렌치를 이용한 소자분리공정을 이용하여 소자분리영역과 게이트전극이 형성될 영역을 동시에 정의함으로써 게이트전극의 채널길이를 증가시켜 소자의 동작 특성을 향상시키는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and in particular, by using a device isolation process using a trench during the manufacturing process of a highly integrated device by defining the device isolation region and the region where the gate electrode will be formed at the same time to increase the channel length of the gate electrode A method of manufacturing a semiconductor device for improving the operating characteristics of the device.
반도체소자가 고집적화되어 감에 따라 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor : 이하 MOS FET라 칭함)의 게이트 전극도 폭이 줄어들고 있으나, 게이트 전극의 폭이 N배 줄어들면 게이트 전극의 전기 저항이 N배 증가되어 반도체소자의 동작 속도를 떨어뜨리는 문제점이 있다.As semiconductor devices become more integrated, gate electrodes of metal oxide semiconductor field effect transistors (hereinafter referred to as MOS FETs) are decreasing in width. There is a problem that the N times increased to decrease the operation speed of the semiconductor device.
일반적으로 반도체 회로를 구성하는 트랜지스터의 기능에서 가장 중요한 기능은 전류구동능력이며, 이를 고려하여 MOS FET의 채널 폭을 조정한다. 가장 널리 쓰이는 MOS FET은 게이트 전극으로 불순물이 도핑된 다결정실리콘층을 사용하고, 소오스/드레인 영역은 반도체기판상에 불순물이 도핑된 확산 영역이 사용된다. 여기서 게이트 전극의 면저항은 약 30∼70Ω/□ 정도이며, 소오스/드레인 영역의 면저항은 N+의 경우에는 약 70∼150Ω/□, P+의 경우 약 100∼250Ω/□ 정도이며, 게이트 전극이나 소오스/드레인 영역 상에 형성되는 콘택의 경우에는 콘택 저항이 하나의 콘택당 약 30∼70Ω/□ 정도이다.In general, the most important function of the transistor constituting the semiconductor circuit is the current driving capability, and the channel width of the MOS FET is adjusted in consideration of this. The most widely used MOS FET uses a polysilicon layer doped with impurities as a gate electrode, and a diffusion region doped with impurities on a semiconductor substrate is used as a source / drain region. Here, the sheet resistance of the gate electrode is about 30 to 70 Ω / □, the sheet resistance of the source / drain region is about 70 to 150 Ω / □ for N +, about 100 to 250 Ω / □ for P +, and the gate electrode or source / In the case of a contact formed on the drain region, the contact resistance is about 30 to 70? /? Per contact.
이와 같이 게이트 전극과 소오스/드레인 영역의 높은 면저항 및 콘택 저항을 감소시키기 위하여 살리사이드(salicide; self-aligned silicide) 방법이나 선택적 금속막 증착 방법으로 게이트전극과 소오스/드레인 영역의 상부에만 금속 실리사이드막을 형성하여 MOS FET의 전류구동능력을 증가시켰다.In order to reduce the high sheet resistance and contact resistance of the gate electrode and the source / drain regions, a metal silicide layer may be formed only on the gate electrode and the source / drain regions using a salicide (self-aligned silicide) method or a selective metal film deposition method. The current driving capability of the MOS FET was increased.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 반도체소자가 고집적화되어감에 따라서 채널의 길이가 서브-쿼터(sub-quarter) 이하로 줄어듦에 따라서 트랜지스터의 쇼트 채널 효과(short channel effect)를 방지하기 위해 임플란트공정수가 증가하고, 열공정의 온도를 조절하기 어려워졌다. 또한, 채널부분에서 누설전류 및 펀치 쓰루(punch through)를 원하는 타겟(target)으로 조절하기 어려워졌다.As described above, in the method of manufacturing a semiconductor device according to the related art, the short channel effect of a transistor is reduced as the length of a channel decreases below a sub-quarter as the semiconductor device becomes highly integrated. To prevent this, the number of implant processes has increased, making it difficult to control the temperature of the thermal process. In addition, it is difficult to adjust the leakage current and punch through to the desired target in the channel portion.
본 발명은 상기한 종래기술의 문제점들을 해결하기 위하여, 트렌치를 이용한 소자분리공정에서 소자분리영역과 게이트전극이 형성될 부분을 동시에 정의하여 트렌치를 형성하고, 매립절연막으로 상기 트렌치를 모두 매립시킨 다음, 상기 게이트전극이 형성될 부분 상에 매립되어 있는 매립절연막을 제거한 후, 게이트절연막 및 다결정실리콘층을 매립한 다음, 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정을 실시하여 게이트전극을 형성하여 트랜지스터의 채널길이를 증가시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, in the device isolation process using a trench, a trench is formed by simultaneously defining a portion where a device isolation region and a gate electrode are to be formed, and filling the trench with a buried insulating film. After removing the buried insulating film buried on the portion where the gate electrode is to be formed, the gate insulating film and the polysilicon layer are buried, followed by chemical mechanical polishing (CMP) process. It is an object of the present invention to provide a method for manufacturing a semiconductor device which is formed to increase the channel length of a transistor.
도 1 내지 도 8 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 8 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체기판 13 : 패드산화막패턴11 semiconductor substrate 13 pad oxide film pattern
15 : 질화막패턴 17 : 소자분리절연막15: nitride film pattern 17: device isolation insulating film
19 : 희생절연막패턴 21 : 제1감광막패턴19: sacrificial insulating film pattern 21: the first photosensitive film pattern
23 : 트렌치 25 : 게이트절연막23 trench 25 gate insulating film
27a : 다결정실리콘층 27b : 게이트전극27a: polysilicon layer 27b: gate electrode
29 : 스크린절연막 31 : LDD영역29 screen insulating film 31 LDD region
33 : 스페이서 34 : 소오스/드레인접합영역33 spacer 34 source / drain junction region
35 : 층간절연막패턴 37 : 확산방지막35: interlayer insulating film pattern 37: diffusion barrier
39 : 금속층 41 : 금속배선콘택39: metal layer 41: metal wiring contact
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 소자분리영역 및 게이트전극으로 예정되는 부분을 노출시키는 절연막패턴을 형성하고, 이를 마스크로 하여 상기 반도체기판에 소자분리막을 형성하는 공정과,상기 게이트전극으로 예정되는 부분의 소자분리막을 식각하는 공정과,전체표면 상부에 게이트절연막과 게이트전극용 도전층을 형성하고, 이를 CMP하여 게이트전극을 형성하는 공정과,Forming an isolation pattern on the semiconductor substrate to expose a portion of the device isolation region and the gate electrode, and forming a isolation layer on the semiconductor substrate using the mask as a mask; Etching, forming a gate insulating film and a conductive layer for the gate electrode on the entire surface, and forming a gate electrode by CMP thereof;
상기 절연막패턴을 제거하여 상기 게이트전극의 측벽을 노출시키는 공정과,상기 게이트전극 측벽에 절연막스페이서를 형성하고, 후속 공정으로 LDD 구조의 소오스/드레인확산영역을 형성하는 공정을 포함하는 것을 특징으로 한다.Removing the insulating film pattern to expose sidewalls of the gate electrode, and forming an insulating film spacer on the sidewall of the gate electrode, and forming a source / drain diffusion region of an LDD structure in a subsequent process. .
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 8 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 to 8 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(11)의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로불순물이 존재하도록한다.First, a desired type of impurity is ion-implanted into a desired portion of the semiconductor substrate 11 so that an impurity exists in a desired form in the channel portion of the well and the transistor and the lower portion of the device isolation region.
다음, 상기 반도체기판(11) 상부에 패드산화막(도시않됨)과 질화막(도시안됨)을 순차적으로 형성하고, 소자분리영역과 게이트전극으로 예정되는 부분을 노출시키는 식각마스크를 이용하여 상기 질화막, 패드산화막 및 반도체기판(11)을 제거해서 질화막패턴(15), 패드산화막패턴(13) 및 트렌치를 형성한다.Next, a pad oxide film (not shown) and a nitride film (not shown) are sequentially formed on the semiconductor substrate 11, and the nitride film and the pad are formed by using an etching mask that exposes portions intended as device isolation regions and gate electrodes. The oxide film and the semiconductor substrate 11 are removed to form the nitride film pattern 15, the pad oxide film pattern 13, and the trenches.
그 다음, 상기 트렌치를 형성하는 공정시 상기 트렌치의 식각면에 발생한 결점을 제거하기 위하여 상기 트렌치의 식각면에 제1열산화막(도시않됨)을 형성하였다가 습식식각방법으로 제거한다.Subsequently, in order to remove defects occurring in the etching surface of the trench during the process of forming the trench, a first thermal oxide layer (not shown) is formed on the etching surface of the trench and then removed by a wet etching method.
그 다음, 상기 트렌치의 식각면에 제2열산화막(도시않됨)을 형성하고, 전체표면 상부에 매립절연막을 형성하여 상기 트렌치를 매립한다. 상기 매립절연막은 고밀도 플라즈마산화막(hign density plasma oxide, HDP) 또는 BPSG(boro phospho silicate glass)막 등을 사용한다.Next, a second thermal oxide film (not shown) is formed on the etching surface of the trench, and a buried insulating film is formed on the entire surface to fill the trench. The buried insulating film may be formed using a high density plasma oxide film (HDP) or a boro phospho silicate glass (BPSG) film.
다음, 상기 매립절연막을 화학기계적 연마(chemical mechanical polishing, 이하 CMP 라함) 방법으로 제거하여 상기 트렌치를 매립시키는 소자분리절연막(17)과 희생절연막패턴(19)을 형성한다. (도 1 참조)Next, the buried insulating film is removed by chemical mechanical polishing (hereinafter referred to as CMP) to form a device isolation insulating film 17 and a sacrificial insulating film pattern 19 for filling the trench. (See Figure 1)
그 다음, 전체표면 상부에 게이트전극으로 예정되는 부분을 노출시키는 감광막패턴(21)을 형성하고, 상기 감광막패턴(21)에 노출되는 상기 희생절연막패턴(19)을 제거하여 반도체기판(11)을 노출시키는 트렌치(23)를 형성한다.Next, a photoresist pattern 21 is formed on the entire surface of the semiconductor substrate 11 to expose a portion intended as a gate electrode, and the sacrificial insulating layer pattern 19 exposed to the photoresist pattern 21 is removed. The trench 23 to be exposed is formed.
다음, 상기 노출된 반도체기판(11)에 문턱전압(Vt)를 조절하기 위한 임플란트공정을 실시한다. (도 2 참조)Next, an implant process for adjusting the threshold voltage Vt is performed on the exposed semiconductor substrate 11. (See Figure 2)
그 다음, 상기 감광막패턴(21)을 제거하고, 전체표면 상부에 게이트절연막(25)을 소정 두께 형성한 다음, 상기 게이트절연막(25) 상부에 게이트전극으로 사용될 다결정실리콘층(27a)을 형성하여 상기 트렌치(23)를 완전히 매립시킨다. 상기 게이트절연막(25)은 N2O 산화막 또는 Al2O5막 등의 물질을 이용하여 형성한다. (도 3 참조)Next, the photoresist pattern 21 is removed, a gate insulating film 25 is formed on the entire surface, and a polysilicon layer 27a to be used as a gate electrode is formed on the gate insulating film 25. The trench 23 is completely buried. The gate insulating film 25 is formed using a material such as an N 2 O oxide film or an Al 2 O 5 film. (See Figure 3)
다음, 상기 질화막패턴(15)을 식각장벽으로한 CMP공정으로 상기 다결정실리콘층(27a)을 제거하여 상기 트렌치(23)를 매립시키는 게이트전극(27b)을 형성한다. (도 4 참조)Next, the polysilicon layer 27a is removed by a CMP process using the nitride film pattern 15 as an etch barrier to form a gate electrode 27b to fill the trench 23. (See Figure 4)
그 다음, 상기 질화막패턴(15) 및 패드산화막패턴(13)을 제거하여 반도체기판(11)을 노출시킨 후, 전체표면 상부에 저농도불순물영역(lightly doped drain, LDD영역)을 형성하기 위하여 스크린절연막(29)을 소정 두께 형성한다. 이때, 스크린절연막(29)을 형성하기 전에 세정공정을 실시하여 상기 소자분리절연막(17)과 반도체기판(11) 간에 단차를 감소시키고, 반도체기판(11)과 게이트전극(27b) 간에 ⓧ 부분과 같이 단차가 형성시킨다. 상기 스크린절연막(29)은 산화막을 사용하여 형성된다.Next, the nitride substrate pattern 15 and the pad oxide layer pattern 13 are removed to expose the semiconductor substrate 11, and then a screen insulating layer is formed to form a lightly doped drain (LDD region) over the entire surface. 29 is formed to a predetermined thickness. At this time, before the screen insulating film 29 is formed, a cleaning process is performed to reduce the step difference between the device isolation insulating film 17 and the semiconductor substrate 11, and to form a gap between the semiconductor substrate 11 and the gate electrode 27b. As step is formed. The screen insulating film 29 is formed using an oxide film.
그 후, 저농도의 n-불순물을 이온주입하여 LDD영역(31)을 형성한다. 이때, NMOS영역에 형성되어 있는 게이트전극에도 동시에 불순물이 이온주입된다. (도 5 참조)Thereafter, a low concentration of n-impurity is implanted to form the LDD region 31. At this time, impurities are implanted into the gate electrode formed in the NMOS region at the same time. (See Figure 5)
다음, 전체표면 상부에 상기 스크린절연막(29)과 식각선택비를 갖는 절연막(도시안됨)을 형성하고, 상기 절연막을 전면식각공정으로 제거하여 도 5 의 ⓧ 부분에 스페이서(33)를 형성한다. 상기 절연막의 형성공정은 전공정에서 손상된 반도체기판(11)을 보상하고, 상기 절연막은 소오스/드레인접합영역을 형성하기 위한 이온주입공정에서 완충역할을 한다.Next, an insulating film (not shown) having an etch selectivity with the screen insulating film 29 is formed on the entire surface, and the insulating film is removed by a front surface etching process to form a spacer 33 in the portion of FIG. 5. The insulating film forming process compensates for the damaged semiconductor substrate 11 in the previous step, and the insulating film plays a buffer role in the ion implantation process for forming the source / drain junction region.
그 다음, 고농도의 불순물을 이온주입하여 소오스/드레인접합영역(34)을 형성한다. 상기 이온주입공정시 NMOS영역에서의 소오스/드레인접합영역과 게이트전극에 고농도의 n+불순물을 동시에 이온주입하고, PMOS영역에서의 소오스/드레인접합영역과 게이트전극에 고농도의 p+불순물을 동시에 이온주입한다. (도 6 참조)Next, a high concentration of impurities are ion implanted to form the source / drain junction region 34. In the ion implantation process, high concentrations of n + impurities are simultaneously implanted into the source / drain junction region and gate electrode in the NMOS region, and high concentrations of p + impurities are simultaneously implanted into the source / drain junction region and gate electrode in the PMOS region. . (See Figure 6)
다음, 전체표면 상부에 층간절연막(도시안됨)을 형성하고, 게이트전극(27b) 및 소오스/드레인접합영역(34)에서 금속배선콘택으로 예정되는 부분을 노출시키는 금속배선콘택마스크를 식각마스크로 상기 층간절연막을 식각하여 금속배선콘택홀이 구비되는 층간절연막패턴(35)을 형성한다.Next, an interlayer insulating film (not shown) is formed over the entire surface, and a metal wiring contact mask exposing a portion intended for the metal wiring contact in the gate electrode 27b and the source / drain junction region 34 is etched. The interlayer insulating layer is etched to form an interlayer insulating layer pattern 35 having a metal wiring contact hole.
그 다음, 전체표면 상부에 확산방지막(37)을 소정 두께 형성하고, 상기 확산방지막(37) 상부에 상기 금속배선콘택홀이 완전히 매립되도록 금속층(39)을 형성한다. 이때, 상기 금속층(39)은 텅스텐층을 이용하여 형성한다. (도 7 참조)Next, a diffusion barrier 37 is formed on the entire surface of the diffusion barrier 37, and a metal layer 39 is formed on the diffusion barrier 37 so as to completely fill the metal wiring contact hole. In this case, the metal layer 39 is formed using a tungsten layer. (See Figure 7)
다음, 상기 금속층(39)과 확산방지막(37)을 CMP공정으로 제거하되, 상기 CMP공정은 상기 층간절연막패턴(35)을 식각장벽으로 사용하여 실시하여 소오스/드레인접합영역(34) 및 게이트전극(27b)에 각각 접속되는 금속배선콘택(41)을 형성한다. (도 8 참조)Next, the metal layer 39 and the diffusion barrier layer 37 are removed by a CMP process, and the CMP process is performed using the interlayer dielectric layer pattern 35 as an etch barrier, so that the source / drain junction region 34 and the gate electrode are removed. Metal wiring contacts 41 connected to the respective 27b are formed. (See Figure 8)
한편, 상기와 같은 반도체소자의 제조방법은 트렌치를 이용한 방법이외에 NSLOCOS방법 또는 PBL(poly buffered LOCOS)방법을 사용할 수도 있다.Meanwhile, the method of manufacturing the semiconductor device as described above may use NSLOCOS method or PBL (poly buffered LOCOS) method in addition to the method using a trench.
이상에서 설명한 바와 같이 본 발명에 따른 듀얼 게이트 제조방법은, 고집적소자의 트랜지스터 제조공정시 트렌치를 이용하여 소자분리영역을 정의하는 공정을 실시할 때 게이트전극으로 예정되는 부분도 동시에 정의하고, 게이트전극이 형성될 부분에 형성되는 절연막을 제거한 다음 게이트전극을 형성하여 게이트전극 하부에 형성되는 채널길이의 증가로 인하여 문턱전압을 감소시킬 수 있으므로 저전압에서도 동작가능한 트랜지스터를 제조함으로써 소자의 고집적화 및 고속화를 유리하게 하는 이점이 있다.As described above, the dual gate manufacturing method according to the present invention simultaneously defines a portion to be a gate electrode when a process of defining a device isolation region using a trench in a transistor manufacturing process of a highly integrated device, and simultaneously defines a gate electrode Since the threshold voltage can be reduced due to the increase in the channel length formed under the gate electrode by removing the insulating film formed on the portion to be formed, the transistor can be operated at low voltage, thereby increasing the integration and speed of the device. There is an advantage to let.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063490A KR100357303B1 (en) | 1999-12-28 | 1999-12-28 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063490A KR100357303B1 (en) | 1999-12-28 | 1999-12-28 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010061015A KR20010061015A (en) | 2001-07-07 |
| KR100357303B1 true KR100357303B1 (en) | 2002-10-19 |
Family
ID=19630819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990063490A KR100357303B1 (en) | 1999-12-28 | 1999-12-28 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100357303B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100798269B1 (en) * | 2002-12-30 | 2008-01-24 | 동부일렉트로닉스 주식회사 | Method For Manufacturing Flash Memory Device |
| CN108155244B (en) * | 2017-12-25 | 2021-10-01 | 深圳市晶特智造科技有限公司 | Groove type grid-connected transistor and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59135768A (en) * | 1983-01-24 | 1984-08-04 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH03154379A (en) * | 1989-11-11 | 1991-07-02 | Takehide Shirato | Semiconductor device |
| JPH03211884A (en) * | 1990-01-17 | 1991-09-17 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| JPH05343676A (en) * | 1992-06-05 | 1993-12-24 | Nec Corp | Field-effect transistor and manufacturing method thereof |
| JPH11150265A (en) * | 1997-11-17 | 1999-06-02 | Toshiba Corp | Semiconductor device |
-
1999
- 1999-12-28 KR KR1019990063490A patent/KR100357303B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59135768A (en) * | 1983-01-24 | 1984-08-04 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH03154379A (en) * | 1989-11-11 | 1991-07-02 | Takehide Shirato | Semiconductor device |
| JPH03211884A (en) * | 1990-01-17 | 1991-09-17 | Matsushita Electron Corp | Semiconductor device and manufacture thereof |
| JPH05343676A (en) * | 1992-06-05 | 1993-12-24 | Nec Corp | Field-effect transistor and manufacturing method thereof |
| JPH11150265A (en) * | 1997-11-17 | 1999-06-02 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010061015A (en) | 2001-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6737308B2 (en) | Semiconductor device having LDD-type source/drain regions and fabrication method thereof | |
| KR20030000074A (en) | Semiconductor device having shared contact and fabrication method thereof | |
| KR20020011133A (en) | Self-aligned source and drain extensions fabricated in a damascene contact and gate process | |
| US6242311B1 (en) | Method of fabricating a semiconductor device with silicided gates and peripheral region | |
| KR20030050995A (en) | Method for fabricating high-integrated transistor | |
| US20010002058A1 (en) | Semiconductor apparatus and method of manufacture | |
| KR20030047371A (en) | A semiconductor device and A method for forming the same | |
| KR20010059976A (en) | Manufacturing method of semiconductor device | |
| KR100293052B1 (en) | Semiconductor device manufacturing method | |
| KR100357303B1 (en) | Manufacturing method of semiconductor device | |
| US7326606B2 (en) | Semiconductor processing methods | |
| KR100212150B1 (en) | Cmos transistor and fabrication method thereof | |
| KR100485004B1 (en) | Soi semiconductor device and method for manufacturing the same | |
| KR100247811B1 (en) | Method for manufacturing semiconductor device | |
| KR980012599A (en) | Methods of forming transistors using salicide process technology | |
| KR100357195B1 (en) | method for forming contact metal line semiconductor device | |
| KR100497194B1 (en) | Method for fabricating gate and silicide of semiconductor device | |
| KR100400780B1 (en) | Method for fabricating of semiconductor device | |
| KR20010065914A (en) | A method for fabricating damascene gate type mos transistor | |
| KR20020096393A (en) | Method for Fabricating MOS transistor | |
| KR100469149B1 (en) | Manufacturing method of semiconductor device | |
| KR20000015244A (en) | Method for fabricating metal oxide semiconductor field effect transistor | |
| KR20010011651A (en) | A method of forming a contact in semiconductor device | |
| KR20000004543A (en) | Method for manufacturing semiconductor devices | |
| KR20020071214A (en) | Semiconductor Device Having Borderless Contact and Method for Fabricating the Same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100920 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |