KR20010011651A - A method of forming a contact in semiconductor device - Google Patents
A method of forming a contact in semiconductor device Download PDFInfo
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- KR20010011651A KR20010011651A KR1019990031124A KR19990031124A KR20010011651A KR 20010011651 A KR20010011651 A KR 20010011651A KR 1019990031124 A KR1019990031124 A KR 1019990031124A KR 19990031124 A KR19990031124 A KR 19990031124A KR 20010011651 A KR20010011651 A KR 20010011651A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 73
- 238000005530 etching Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 23
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims description 27
- 239000012535 impurity Substances 0.000 claims description 21
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 79
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000002955 isolation Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000004380 ashing Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 반도체제조공정중 감소된 디자인 룰과 증가된 소자의 집적도에 기인한 활성영역위에 형성되는 콘택홀의 공정 마진을 확보하기 위하여 종래의 식각방지막을 추가로 형성하는 대신 게이트 측벽 스페이서 형성용 절연막을 설계치 보다 두껍게 형성한 다음 에치백을 절연막이 기판 표면에 얇게 잔류하도록 형성하므로서 게이트 측벽 스페이서와 불순물 도핑시 버퍼막 및 식각정지막을 하나의 절연막으로 형성하도록하여 콘택홀 식각시 활성영역 및 필드산화막의 손실을 방지하여 소자의 리프레쉬 특성을 향상시키는 반도체장치의 콘택형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a conventional anti-etching film is added to secure a process margin of a contact hole formed over an active region due to reduced design rules and increased device integration during a semiconductor manufacturing process. Instead of forming a thin film, the insulating film for forming the gate sidewall spacers is formed thicker than the designed value, and then the etch back is formed so that the insulating film remains thinly on the substrate surface. The present invention relates to a method for forming a contact in a semiconductor device which prevents loss of an active region and a field oxide layer during contact hole etching, thereby improving refresh characteristics of the device.
일반적인 트렌치 격리방법에 있어서, 트렌치는 상호 격리될 필요가 있는 활성영역 사이에 전기적 절연을 위한 산화막 등으로 채워져서 형성된다. 이후, 트랜지스터 등을 포함하는 소자들이 소정의 활성영역 또는 트렌치 상부에 걸쳐서 형성된다.In a typical trench isolation method, the trench is formed by filling an oxide film or the like for electrical insulation between active regions that need to be insulated from each other. Thereafter, elements including transistors and the like are formed over a predetermined active region or over the trench.
트렌치 격리방법에 있어서의 문제점은 트렌치 영역위에 보더리스 콘택을 형성하는 것이다. 이때, 보더리스 콘택(borderless contact)이란 반도체기판 위에 형성된 활성영역과 격리영역에 걸쳐서 형성되는 콘택을 말한다. 이러한 문제점은 층간절연층을 식각하여 콘택홀을 형성할 때 트렌치 격리영역이 손상되지 않도록 유지하기 곤란한데 있다.A problem with the trench isolation method is the formation of borderless contacts over the trench region. In this case, the borderless contact refers to a contact formed over an active region and an isolation region formed on a semiconductor substrate. This problem is difficult to maintain the trench isolation region from being damaged when the interlayer insulating layer is etched to form a contact hole.
일반적인 콘택홀 형성시, 활성영역 상에 형성되는 콘택홀의 싸이즈가 게이트와 필드산화막 사이의 활성영역상에 충분히 위치할 수 있는 공간에 적합하면 다이렉트 콘택을 형성하므로서, 필드산화막의 손실을 전혀 고려할 필요가 없다. 따라서 콘택홀은 필드산화막과 오버랩(overlap)되는 부위가 전혀 없이 단지 활성영역상에만 위치하게 된다. 실제로, 활성영역이 실리콘 졍션이거나 Co, Ti 등의 살리사이드일 경우에도 활성영역과 필드산화막의 경계부가 콘택홀 형성을 위한 식각시 식각제로 부터 공격을 받지 않으므로 필드산화막의 손실이 없으며 활성영역과 필드영역의 경계부위에서도 누설전류가 발생하지 않게 된다.In forming a general contact hole, if the size of the contact hole formed on the active region is suitable for a space that can be sufficiently located on the active region between the gate and the field oxide film, direct contact is formed, so that no loss of the field oxide film needs to be considered. none. Therefore, the contact hole is located only on the active region without any overlapping area with the field oxide layer. In fact, even when the active region is a silicon cushion or a salicide such as Co or Ti, the boundary between the active region and the field oxide layer is not attacked by the etchant during etching to form the contact hole, so there is no loss of the field oxide layer and the active region and the field. The leakage current does not occur even at the boundary of the region.
그러나, 보더리스 콘택 형성공정에서, 콘택홀의 싸이즈와 비교하여 필드영역과 게이트 라인 사이의 활성영역의 크기가 상대적으로 작은 경우와 콘택홀이 필드산화막과 활성영역에 걸쳐서 형성된 경우에는 층간절연층 식각시 오버랩되는 필드산화막의 손실이 과도식각때문에 발생하게 된다. 이러한 경우, 셀의 격리 문제 뿐만 아니라 과도식각된 부위에서 노출된 기판의 실리콘이 식각시 플라즈마로 부터 손상을 입게 되어 누설전류가 발생된다. 따라서, 필드산화막을 보호할 수 있는 질화막을 게이트라인 형성 후 또는 활성영역 위에 살리사이드를 형성한 후 필드산화막 위에 증착하게 된다.However, in the borderless contact forming process, when the size of the active region between the field region and the gate line is relatively small compared to the size of the contact hole and when the contact hole is formed over the field oxide layer and the active region, the interlayer insulating layer is etched. Loss of overlapping field oxide film is caused by transient etching. In this case, as well as the isolation problem of the cell, the silicon of the substrate exposed at the over-etched portion is damaged from the plasma during etching, resulting in leakage current. Therefore, a nitride film that can protect the field oxide film is deposited on the field oxide film after the gate line is formed or after the salicide is formed on the active region.
일반적인 콘택 형성시에는 콘택홀 식각 후 별도의 식각방지층(stopping layer)이 없으므로 별 문제가 없으나, 보더리스 콘택 형성시에는 층간절연층을 식각한 후에 별도의 질화막 식각공정이 필요하게 된다. 이때, 질화막 식각에 대하여 실리콘 및 살리사이드와의 높은 식각선택비가 요구된다.When forming a general contact, there is no problem because there is no separate etching layer after the contact hole etching, but when forming the borderless contact, a separate nitride layer etching process is required after etching the interlayer insulating layer. In this case, a high etching selectivity with silicon and salicide is required for the nitride film etching.
종래 기술들은 모두 식각방지층을 식각하는 방법이나 필드산화막을 이용한 격리방법을 보호해주는 별도의 층의 형성에 관한 것이다. 그러나, 이들이 제시하는 내용들은 별도의 식각방지층을 필드산화막 위에 형성한 다음 콘택홀 형성용 건식식각에서 산화막 식각 후 추가로 식각방지층을 식각하는 공정이거나, 소자격리를 위한 트렌치 형성용 식각 후 트렌치 매립 단계 전에 활성영역의 실리콘을 보호하기 위한 별도의 층을 미리 증착하여 씨엠피 공정(Chemical-Mechanical Polishing) 공정을 사용하는 방법 뿐이다.The related arts all relate to the formation of a separate layer that protects the etching method or the isolation method using the field oxide film. However, they suggest that a separate etch stop layer is formed on the field oxide layer and then the etching step is additionally etched after the oxide layer is etched in the dry etching for forming the contact hole, or the trench filling step after the trench formation for device isolation is performed. The only method is to use a chemical-mechanical polishing process by previously depositing a separate layer to protect silicon in the active region.
도 1a 내지 도 1d 는 종래 기술에 따른 반도체장치의 콘택 형성방법을 도시하는 공정단면도이다.1A to 1D are cross-sectional views showing a method for forming a contact of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체기판(10)인 실리콘기판(10)의 소정 부분을 포토리쏘그래피로 식각하여 활성영역과 필드영역을 한정하는 트렌치를 형성한 후, 트렌치를 매립하는 산화막(11)을 형성한다. 이때, 트렌치를 매립하는 방법은 트렌치를 포함하는 실리콘기판(10)의 전면에 증착하여 형성한 후 에치백하여 형성한다. 이와 같이 형성된 매립산화막(11)의 상부 가장자리 부위는 물리적 특성상 약간 과도식각되어 얕은 홈을 형성하게 된다.Referring to FIG. 1A, a portion of the silicon substrate 10, which is the semiconductor substrate 10, is etched by photolithography to form a trench defining an active region and a field region, and then an oxide film 11 filling a trench is formed. Form. In this case, the method of filling the trench is formed by depositing the entire surface of the silicon substrate 10 including the trench and then etching back. The upper edge portion of the buried oxide film 11 formed as described above is slightly overetched to form a shallow groove due to physical characteristics.
그 다음 노출된 기판(10)의 전면에 게이트산화막(12)을 형성한 후, 그 위에 게이트 형성용으로 불순물이 도핑된 폴리실리콘층(13)을 증착하여 형성한 다음 그(13) 위에 캡핑용 절연막(14)으로 질화막(14)을 증착하여 형성한다.Thereafter, a gate oxide film 12 is formed on the entire surface of the exposed substrate 10, and then a polysilicon layer 13 doped with impurities is formed thereon for forming a gate thereon, and then capped thereon. The nitride film 14 is formed by depositing the insulating film 14.
그리고, 질화막(14)/폴리실리콘층(13)/게이트산화막(12)을 차례로 패터닝하여 게이트패턴(14,13,12)을 형성한 다음, 전면에 산화막을 증착한 후 에치백하여 게이트패턴(14,13,12)의 측면에 잔류한 산화막으로 이루어진 측벽 스페이서(15)를 형성한다. 도시되지는 않았지만, 게이트패턴 형성 후 전면에 저농도 이온주입을 실시하여 게이트(13) 모서리 하단에 위치하는 기판(10) 부위에 엘디디(lightly doped drain)영역을 위한 저농도 불순물 매몰층을 형성한다.Then, the nitride film 14, the polysilicon layer 13, and the gate oxide film 12 are patterned in order to form the gate patterns 14, 13, and 12. Then, an oxide film is deposited on the entire surface and then etched back to form a gate pattern ( Sidewall spacers 15 made of the oxide film remaining on the side surfaces 14, 13, and 12 are formed. Although not shown, low concentration ion implantation is performed on the entire surface after the gate pattern is formed to form a low concentration impurity buried layer for the lightly doped drain region in the portion of the substrate 10 positioned at the bottom edge of the gate 13.
측벽 스페이서(15) 형성후, 트랜지스터의 소스/드레인 형성용 이온주입을 고농도로 실시하여 소스/드레인영역(16)을 형성한 다음, 노출된 소스/드레인영역(16) 위에 전기적 저항을 감소시키기 위한 실리사이드층(도시안함)을 형성한다.After the sidewall spacers 15 are formed, ion implantation for source / drain formation of the transistor is performed at a high concentration to form the source / drain regions 16 and thereafter, to reduce the electrical resistance on the exposed source / drain regions 16. A silicide layer (not shown) is formed.
따라서, 트랜지스터의 제조가 완료된다.Thus, the manufacture of the transistor is completed.
도 1b를 참조하면, 실리사이드층, 트랜지스터, 필드산화막(11)을 포함하는 기판(10)의 전면에 질화막(18)을 증착하여 형성한다. 질화막(18)은 보더리스 콘택 형성을 위한 식각공정시 산화막, 실리콘 그리고 살리사이드와의 식각선택비가 높은 물질로서 이후 콘택홀 형성공정을 두 단계로 나누어 실시하게 하는 식각방지층인 배리어층(18)으로서의 역할을 수행하게 한다.Referring to FIG. 1B, the nitride film 18 is deposited on the entire surface of the substrate 10 including the silicide layer, the transistor, and the field oxide film 11. The nitride film 18 is a material having a high etching selectivity with respect to oxide film, silicon, and salicide in the etching process for forming a borderless contact, and then acts as a barrier layer 18, which is an etch preventing layer, which is performed in two steps. Have a role.
도 1c를 참조하면, 질화막(18)의 전면에 소자의 보호 및 평탄화를 위한 층간절연막(19)으로 산화막(19)을 두껍게 형성한 다음, 층간절연막(19) 위에 포토레지스트를 도포한 후 보더리스 콘택 부위를 한정하는 마스크를 이용한 노광 및 현상을 실시하여 보더리스 콘택 상부의 층간절연막(19) 표면을 노출시키는 포토레지스트패턴(20)을 형성한다.Referring to FIG. 1C, a thick oxide film 19 is formed on the entire surface of the nitride film 18 with an interlayer insulating film 19 for protection and planarization of the device, and then a photoresist is applied on the interlayer insulating film 19 and then borderless. Exposure and development using a mask defining a contact portion are performed to form a photoresist pattern 20 exposing the surface of the interlayer insulating film 19 over the borderless contact.
도 1d를 참조하면, 포토레지스트패턴(20)을 식각마스크로 이용한 일차 건식식각을 노출된 층간절연막(19)에 실시하여 포토레지스트패턴(20)으로 부터 보호되지 아니하는 부위의 층간절연막(19)을 제거하여 질화막(18)의 일부 표면을 노출시킨다. 이때, 식각제로는 C2F6를 사용한다.Referring to FIG. 1D, the first interlayer insulating film 19 using the photoresist pattern 20 as an etching mask is applied to the exposed interlayer insulating film 19 so as to protect the interlayer insulating film 19 from a portion not protected from the photoresist pattern 20. Is removed to expose a portion of the surface of the nitride film 18. At this time, C 2 F 6 is used as an etchant.
그 다음, 포토레지스트패턴을 산소 애슁(O2ashing) 등의 방법으로 제거한다.Then, the photoresist pattern is removed by a method such as oxygen ashing (O 2 ashing).
계속하여 노출된 질화막(18)에 이차 건식식각을 실시하여 소스/드레인 영역(16) 또는 실리사이드층의 일부 표면과 트렌치에 형성된 필드산화막(11)의 일부 표면을 노출시키는 콘택홀을 형성한다. 이때, 이차 식각은 C2F6와 O2를 사용한다. 따라서, 이와 같이 형성된 콘택홀을 보더리스 콘택홀이라 하는데, 이는 콘택홀이 필드산화막(11) 일부와 소스/드레인 영역의 일부에 걸쳐서 형성되었기 때문이다.Subsequently, the exposed nitride film 18 is subjected to secondary dry etching to form a contact hole exposing a portion of the source / drain region 16 or the silicide layer and a portion of the field oxide film 11 formed in the trench. In this case, secondary etching uses C 2 F 6 and O 2 . Therefore, the contact hole thus formed is called a borderless contact hole because the contact hole is formed over a part of the field oxide film 11 and a part of the source / drain region.
그러나, 상술한 종래 기술에 따른 반도체장치의 콘택 형성방법은 질화막 식각시 노출되는 필드산화막의 손실이 발생하게 되고, 이러한 경우, 셀의 격리 문제 뿐만 아니라 과도식각된 부위에서 노출된 기판의 실리콘이 식각시 플라즈마로 부터 손상을 입게 되어 누설전류가 발생되는 문제점이 있다.However, the contact forming method of the semiconductor device according to the related art described above causes loss of the field oxide film exposed during etching of the nitride film. In this case, not only the isolation of the cell but also the silicon of the substrate exposed from the overetched portion is etched. There is a problem in that leakage current is generated due to damage from the plasma.
따라서, 본 발명의 목적은 반도체제조공정중 감소된 디자인 룰과 증가된 소자의 집적도에 기인한 활성영역위에 형성되는 콘택홀의 공정 마진을 확보하기 위하여 종래의 식각방지막을 추가로 형성하는 대신 게이트 측벽 스페이서 형성용 절연막을 설계치 보다 두껍게 형성한 다음 에치백을 절연막이 기판 표면에 얇게 잔류하도록 형성하므로서 게이트 측벽 스페이서와 불순물 도핑시 버퍼막 및 식각정지막을 하나의 절연막으로 형성하도록하여 콘택홀 식각시 활성영역 및 필드산화막의 손실을 방지하여 소자의 리프레쉬 특성을 향상시키는 반도체장치의 콘택형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a gate sidewall spacer instead of additionally forming a conventional etch stop layer to secure a process margin of a contact hole formed over an active region due to reduced design rules and increased device integration during a semiconductor manufacturing process. After forming the insulating film thicker than the designed value, the etch back is formed so that the insulating film remains thinly on the substrate surface, so that the buffer layer and the etch stop film are formed as one insulating film when the gate sidewall spacer and the impurity dopants are formed. Disclosed is a method for forming a contact in a semiconductor device which prevents loss of field oxide film and improves refresh characteristics of the device.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 콘택 형성방법은 제 1 도전형 반도체 기판의 소정 부위에 활성영역과 필드영역을 정의하는 필드절연막을 형성하는 단계와, 활성영역에 게이트절연막이 개재된 게이트패턴을 형성하는 단계와, 게이트패턴 측면 하부의 활성영역에 저농도 불순물 확산영역을 형성하는 단계와, 게이트패턴을 포함하는 반도체기판의 전면에 필드절연막과 식각선택성이 큰 물질로 이루어진 제 1 절연막을 소정 두께로 형성하는 단계와, 제 1 절연막에 비등방성 식각을 실시하여 필드절연막과 활성영역에 소정의 두께로 잔류시키고 동시에 게이트패턴의 측면에 잔류한 제 1 절연막으로 이루어진 측벽 스페이서를 형성하는 단계와, 측벽 스페이서 부근의 활성영역에 고농도 불순물 확산영역을 형성하는 단계와, 잔류한 제 1 절연막의 전면에 제 1 절연막과 식각선택성이 있는 물질로 층간절연층을 형성하는 단계와, 층간절연층과 제 1 절연막의 소정 부위를 제거하여 필드절연막과 고농도 불순물 확산영역의 표면을 동시에 노출시키는 콘택홀을 형성하는 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of forming a contact for a semiconductor device, the method including: forming a field insulating film defining an active region and a field region in a predetermined portion of a first conductivity type semiconductor substrate; Forming a gate pattern; forming a low concentration impurity diffusion region in an active region below the side of the gate pattern; and a first insulating layer formed of a material having a high etch selectivity and a field insulating film on the entire surface of the semiconductor substrate including the gate pattern. Forming an insulating film to a predetermined thickness, and performing anisotropic etching on the first insulating film to form a sidewall spacer comprising a first insulating film remaining on the side of the gate pattern and remaining at a predetermined thickness in the field insulating film and the active region. Forming a high concentration impurity diffusion region in the active region near the sidewall spacers; Forming an interlayer insulating layer with a material having an etch selectivity and a first insulating film on the entire surface of the first insulating film, and simultaneously removing the predetermined portions of the interlayer insulating layer and the first insulating film to expose the surface of the field insulating film and the high concentration impurity diffusion region. And forming a contact hole.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 콘택 형성방법을 도시하는 공정단면도1A to 1D are process cross-sectional views illustrating a method for forming a contact in a semiconductor device according to the prior art;
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 콘택 형성방법을 도시하는 공정단면도2A to 2D are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to the present invention.
본 발명은 종래 식각시 손상을 방지하기 위한 식각정지층으로 절연층을 추가로 형성하는 대신 게이트 측벽 스페이서 형성용 절연막을 두껍게 형성하고 이를 이방성식각인 에치백으로 측벽 스페이서를 형성할 때 절연막을 기판 표면에서 완전히 제거하지 않고 소정 두께로 잔류하도록하여 상기한 목적을 달성한다.In the present invention, instead of forming an insulating layer as an etch stop layer to prevent damage during conventional etching, the insulating film for forming the gate sidewall spacers is thickly formed and when the sidewall spacers are formed with an anisotropic etch back, the insulating film is formed on the substrate surface. The above object is achieved by remaining at a predetermined thickness without completely removing it.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 콘택 형성방법을 도시하는 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of forming a contact in a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판(30)인 실리콘기판(30)의 소정 부분을 포토리쏘그래피로 식각하여 활성영역과 필드영역을 한정하는 트렌치를 형성한 후, 트렌치를 매립하는 필드산화막(31)을 형성한다. 이때, 트렌치를 매립하는 방법은 트렌치를 포함하는 실리콘기판(30)의 전면에 증착하여 형성한 후 에치백하여 형성한다. 이와 같이 형성된 매립산화막(31)의 상부 가장자리 부위는 물리적 특성상 약간 과도식각되어 얕은 홈을 형성하게 된다.Referring to FIG. 2A, a predetermined portion of the silicon substrate 30, which is the semiconductor substrate 30, is etched by photolithography to form a trench that defines an active region and a field region, and then fills the trench with a field oxide layer 31. To form. In this case, the method of filling the trench is formed by depositing the entire surface of the silicon substrate 30 including the trench and then etching back. The upper edge portion of the buried oxide film 31 formed as described above is slightly overetched to form a shallow groove due to physical characteristics.
그 다음 노출된 기판(30)의 전면에 게이트산화막(32)을 형성한 후, 그 위에 게이트 형성용으로 불순물이 도핑된 폴리실리콘층(33)을 증착하여 형성한 다음 그(33) 위에 캡핑용 절연막(34)으로 질화막(34)을 증착하여 형성한다.Next, after the gate oxide film 32 is formed on the entire surface of the exposed substrate 30, an impurity doped polysilicon layer 33 is formed thereon to form a gate thereon, and then a capping layer is formed thereon. The nitride film 34 is formed by depositing the insulating film 34.
그리고, 질화막(34)/폴리실리콘층(33)/게이트산화막(32)을 차례로 패터닝하여 게이트패턴(34,33,32)을 형성한다.The nitride film 34 / polysilicon layer 33 / gate oxide film 32 is patterned in order to form gate patterns 34, 33, and 32.
그다음, 저농도 도핑된 불순물이온 확산영역(lightly doped drain, LDD)을 형성하기 위하여 게이트패턴을 마스크로 이용하는 이온주입을 실시하여 게이트패턴 측면 하단부의 활성영역에 저농도 불순물 확산영역(도시안함)을 형성한다. 이러한 엘디디 구조는 선택사항이다.Subsequently, ion implantation using a gate pattern as a mask is performed to form a lightly doped impurity diffusion region (LDD) to form a low concentration impurity diffusion region (not shown) in the active region at the lower side of the gate pattern. . This LED structure is optional.
그리고, 기판의 전면에 절연막(36)으로 질화막(36)을 화학기상증착법(chemical vapor deposition)으로 증착한다. 이때, 증착되는 질화막(36)은 게이트(33)의 측면을 절연시키는 게이트 측벽 스페이서와 필드산화막(31)의 식각보호용 식각정지막과 고농도 불순물 확산영역 형성용 이온주입시 활성영역의 기판을 보호하는 버퍼막 등으로 다양하게 이용된다.Then, the nitride film 36 is deposited by chemical vapor deposition on the entire surface of the substrate with the insulating film 36. In this case, the deposited nitride layer 36 may protect the substrate of the active region when the gate sidewall spacer insulating the side surface of the gate 33, the etch stop layer for etching the field oxide layer 31, and the ion implantation for forming a high concentration impurity diffusion region. It is variously used as a buffer film.
도 2b를 참조하면, 다양한 용도로 이용될 질화막(36)에 비등방성 식각으로 에치백을 실시한다. 이때, 에치백은 질화막이 활성영역과 필드산화막(31)의 표면에 얇게 잔류할 정도로 제어하여 실시한다. 따라서, 에치백된 질화막(34) 중 게이트패턴(34,33,32) 측면에 잔류한 질화막(360)부위는 측벽 스페이서(sidewall spacer)가 되고, 활성영역 표면 및 필드산화막(31) 표면에 잔류한 질화막(360)은 콘택홀 식각시 식각정지막으로 이용되며, 특히, 활성영역의 표면에 잔류한 질화막은 소스/드레인 영역 형성용 고농도 이온 주입시 활성영역의 손상을 방지하는 이온주입 버퍼막(buffer layer)으로 작용한다.Referring to FIG. 2B, the nitride film 36 to be used for various purposes is etched back by anisotropic etching. At this time, the etch back is controlled so that the nitride film remains thinly on the surface of the active region and the field oxide film 31. Therefore, the nitride film 360 remaining on the side surfaces of the gate patterns 34, 33, and 32 of the etched nitride film 34 becomes a sidewall spacer and remains on the surface of the active region and the surface oxide film 31. One nitride layer 360 is used as an etch stop layer during contact hole etching, and in particular, the nitride layer remaining on the surface of the active region is an ion implantation buffer layer that prevents damage of the active region during high concentration ion implantation for forming source / drain regions. buffer layer).
그리고, 활성영역 상부에 위치한 잔류한 질화막(360)을 이온주입 버퍼막으로 이용하는 불순물 이온주입을 고농도로 실시하여 곤??도 불순물 확산영역을 형성하므로서 저농도 불순물 확산영역과 더불어 소스/드레인영역(35)을 완성한다. 그리고, 노출된 소스/드레인영역(35) 위에 전기적 저항을 감소시키기 위한 실리사이드층(도시안함)을 형성한다. 이는, 선택사항이다.In addition, the impurity ion implantation using the remaining nitride film 360 positioned above the active region as the ion implantation buffer film is performed at a high concentration to form the high concentration impurity diffusion region, and thus the source / drain region 35 together with the low concentration impurity diffusion region. To complete). A silicide layer (not shown) is formed on the exposed source / drain regions 35 to reduce electrical resistance. This is optional.
따라서, 트랜지스터의 제조가 완료된다.Thus, the manufacture of the transistor is completed.
도 2c를 참조하면, 잔류한 질화막(32) 표면에 HLD(high temperature low pressure dielectric)과 평탄화성이 좋은 BPSG(boron phosphor silicate glass) 등을 차례로 증착하여 표면이 평탄화된 층간절연층(37)을 두껍게 형성한다.Referring to FIG. 2C, a high temperature low pressure dielectric (HLD) and boron phosphor silicate glass (BPSG) having good planarization are sequentially deposited on the remaining nitride film 32 to form an interlayer insulating layer 37 having a planarized surface. Form thickly.
그리고, 층간절연층(37) 위에 포토레지스트를 도포한 후 콘택 부위를 한정하는 마스크를 이용한 노광 및 현상을 실시하여 보더리스 콘택 상부의 층간절연층(37) 표면을 노출시키는 포토레지스트패턴(300)을 형성한다.After the photoresist is applied on the interlayer insulating layer 37, the photoresist pattern 300 exposing and exposing the surface of the interlayer insulating layer 37 on the borderless contact by performing exposure and development using a mask defining a contact portion. To form.
포토레지스트패턴(300)을 식각마스크로 이용한 일차 건식식각을 노출된 층간절연층에 실시하여 포토레지스트패턴(300)으로 부터 보호되지 아니하는 부위의 층간절연층을 제거하여 잔류한 질화막(360)의 일부 표면을 노출시키는 콘택홀(H)을 형성한다. 이때, 식각제로는 C2F6를 사용한다.The first dry etching using the photoresist pattern 300 as an etch mask is performed on the exposed interlayer insulating layer to remove the interlayer insulating layer of a portion which is not protected from the photoresist pattern 300, thereby remaining of the nitride film 360. A contact hole H exposing a portion of the surface is formed. At this time, C 2 F 6 is used as an etchant.
그 다음, 포토레지스트패턴을 산소 애슁(O2ashing) 등의 방법으로 제거한다.Then, the photoresist pattern is removed by a method such as oxygen ashing (O 2 ashing).
도 2d를 참조하면, 노출된 질화막(360)에 이차 건식식각을 실시하여 소스/드레인 영역(35) 또는 실리사이드층의 일부 표면과 트렌치에 형성된 필드산화막(31)의 일부 표면을 노출시킨다. 이때, 이차 식각은 C2F6와 O2를 사용한다. 따라서, 이와 같이 형성된 콘택홀을 보더리스 콘택홀이라 하는데, 이는 콘택홀이 필드산화막(31) 일부와 소스/드레인영역(35)의 일부에 걸쳐서 형성되었기 때문이다.Referring to FIG. 2D, a second dry etching is performed on the exposed nitride layer 360 to expose a portion of the source / drain region 35 or the silicide layer and a portion of the field oxide layer 31 formed in the trench. In this case, secondary etching uses C 2 F 6 and O 2 . Therefore, the contact hole thus formed is called a borderless contact hole because the contact hole is formed over a part of the field oxide film 31 and a part of the source / drain region 35.
이후, 도시되지는 않았으나 텅스텐 등의 도전체로 콘택홀을 충전하는 플러그를 형성한 다음, 플러그 표면 및 층간절연층 위에 층간 배선층을 형성한 다음 패터닝하여 소자들을 전기적으로 연결하는 층간배선 또는 캐패시터 등의 소자를 형성한다.Subsequently, although not shown, a plug for filling a contact hole with a conductor such as tungsten is formed, an interlayer wiring layer is formed on the surface of the plug and the interlayer insulating layer, and then patterned to electrically connect the devices. To form.
따라서, 본 발명은 게이트 측벽 스페이서 형성용 절연막을 설계치 보다 두껍게 형성한 다음 에치백을 절연막이 기판 표면에 얇게 잔류하도록 형성하므로서 게이트 측벽 스페이서와 불순물 도핑시 버퍼막 및 식각정지막을 하나의 절연막으로 형성하도록하여 콘택홀 식각시 활성영역 및 필드산화막의 손실을 방지하여 소자의 리프레쉬 특성을 향상시키는 장점이 있다.Therefore, the present invention forms the insulating film for forming the gate sidewall spacers thicker than the design value, and then forms the etch back so that the insulating film remains thinly on the substrate surface so that the buffer sidewall and the etch stop layer are formed as one insulating film when doping the gate sidewall spacer and the impurity. Therefore, it is possible to prevent the loss of the active region and the field oxide layer during the contact hole etching, thereby improving the refresh characteristics of the device.
Claims (5)
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| KR1019990031124A KR20010011651A (en) | 1999-07-29 | 1999-07-29 | A method of forming a contact in semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030056607A (en) * | 2001-12-28 | 2003-07-04 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100400308B1 (en) * | 2001-03-28 | 2003-10-01 | 주식회사 하이닉스반도체 | A method for forming a borderless contact of a semiconductor device |
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1999
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400308B1 (en) * | 2001-03-28 | 2003-10-01 | 주식회사 하이닉스반도체 | A method for forming a borderless contact of a semiconductor device |
| KR20030056607A (en) * | 2001-12-28 | 2003-07-04 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
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