JPS6266679A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6266679A JPS6266679A JP20752085A JP20752085A JPS6266679A JP S6266679 A JPS6266679 A JP S6266679A JP 20752085 A JP20752085 A JP 20752085A JP 20752085 A JP20752085 A JP 20752085A JP S6266679 A JPS6266679 A JP S6266679A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- melting point
- high melting
- point metal
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title description 3
- 238000002844 melting Methods 0.000 claims abstract description 44
- 230000008018 melting Effects 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 35
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 238000003746 solid phase reaction Methods 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910008479 TiSi2 Inorganic materials 0.000 abstract description 3
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 11
- 239000010936 titanium Substances 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000003870 refractory metal Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔）概要〕
高融点金属の固相反応を用いてゲート電極、およびソー
ス、ドレイン領域′上に高融点金属シリサイド層を形成
する際に、ゲート電極上の高融点金属シリサイド層の層
抵抗値を、ソース、ドレイン領域上のそれより小さくし
て集積回路の配線抵抗を引き下げて高速化をはかるため
、ゲート上に前もって高融点金属シリサイド層を敷くこ
とにより目的を達する。Detailed Description of the Invention [) Overview] When a high melting point metal silicide layer is formed on the gate electrode and the source and drain regions using a solid phase reaction of the high melting point metal, the high melting point metal on the gate electrode is In order to lower the interconnect resistance of the integrated circuit and increase its speed by making the layer resistance value of the silicide layer smaller than that of the source and drain regions, this objective is achieved by pre-laying a refractory metal silicide layer on the gate.
本発明は高融点金属の固相反応を用いてゲート電極、お
よびソース、ドレイン領域上に高融点金属シリサイド層
を形成する工程を含む半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device including a step of forming a high melting point metal silicide layer on a gate electrode and source and drain regions using a solid phase reaction of a high melting point metal.
従来、ゲート電極は多結晶珪素（ポリＳｉ）で形成され
、かつ延長して配線に用いられているため、配線抵抗値
を引き下げる必要がある。そのためケート電極はポリサ
イドと呼ばれる、ポリＳｉ上に高融点金属シリサイドを
被着した複合層が用いられることがある。Conventionally, gate electrodes are formed of polycrystalline silicon (poly-Si) and are extended to be used as interconnects, so it is necessary to reduce the interconnect resistance value. For this reason, a composite layer called polycide, in which high-melting point metal silicide is deposited on poly-Si, is sometimes used for the gate electrode.
最近、集積回路の高集積化、高速化の要望より素子が微
細化され、ソース、ドレイン領域も浅く（７ｙｔ＜）な
り、従って層抵抗は１００Ω／口程度と大きくなるため
、これを補い、かつ電極とのコンタクトをよくするため
にソース、ドレイン領域上にも高融点金属シリサイドを
形成することが検討されている。Recently, due to the demand for higher integration and higher speed of integrated circuits, elements have been miniaturized, and the source and drain regions have become shallower (<7yt), so the layer resistance has increased to about 100 Ω/hole. Consideration has been given to forming refractory metal silicide on the source and drain regions to improve contact with the electrodes.
この場合、ソース、ドレイン領域上の高融点金属シリサ
イド層の層抵抗値は数Ω／口でよいが、配線を兼ねるゲ
ート電極上のそれは１９７口以下を狙うため、高融点金
属シリサイド層形成のための高融点金属層を厚く被着し
なければならず、大きなストレスを基板にあたえ、ゲー
トとソース、ドレインがショートすることになり、その
対策が要望されている。In this case, the layer resistance value of the high melting point metal silicide layer on the source and drain regions may be a few Ω/hole, but the layer resistance value on the gate electrode, which also serves as wiring, is aimed at 197 or less. A thick high-melting point metal layer must be applied to the substrate, which places a large stress on the substrate, resulting in short circuits between the gate, source, and drain, and countermeasures are needed.
第２図（１１〜（４）はゲート電極、およびソース、ト
レイン領域上に高融点金属シリサイド層を形成する従来
例による方法を工程順に説明する断面図である。FIGS. 2(11-4) are cross-sectional views illustrating, in order of process, a conventional method for forming a high melting point metal silicide layer on the gate electrode, source, and train regions.
第２図（１）において、１は半導体基板、例えばｐ型珪
素（ｐ−Ｓｉ）基板で、この上に熱酸化により厚さ２０
０〜５００人のゲート酸化膜２、化学気相成長（ＣＶＤ
）法により厚さ５０００人のポリＳｉ層３を順次被着し
、通常のフォトプロセスを用いてこれらの層をパターニ
ングしてゲート電極を形成する。In FIG. 2 (1), 1 is a semiconductor substrate, for example, a p-type silicon (p-Si) substrate, on which a thickness of 20 mm is deposited by thermal oxidation.
0-500 gate oxide film 2, chemical vapor deposition (CVD)
) poly-Si layers 3 with a thickness of 5,000 wafers are sequentially deposited by the method, and these layers are patterned using a conventional photo process to form the gate electrode.
つぎに、ゲート電極をマスクにして、イオン注入により
ｎ゛型のソース、ドレイン領域１１１２を形成する。Next, using the gate electrode as a mask, n-type source and drain regions 1112 are formed by ion implantation.
第２図（２）において、ＣＶＤ法により、ゲート電極を
覆って基板上全面に厚さ２０００〜４０００人の二酸化
珪素（ＳｉＯ□）ｌ’ｉを被着し、リアクティブイオン
エツチング（ＲＩＥ）法による垂直方向に優勢な異方性
エツチングを用いてＳｉＯ□サイドウオール５を形成す
る。In FIG. 2 (2), silicon dioxide (SiO□) l'i is deposited to a thickness of 2000 to 4000 on the entire surface of the substrate, covering the gate electrode, by CVD, and then etched by reactive ion etching (RIE). The SiO□ sidewall 5 is formed using vertically dominant anisotropic etching.
第２図（３）において、スパ７．夕法により、基板全面
に高融点金属層として厚さ３００人のチタン（Ｔｉ）層
６を被着する。In FIG. 2 (3), spa 7. A titanium (Ti) layer 6 with a thickness of 300 nm is deposited as a high melting point metal layer over the entire surface of the substrate by a method.
第２図（４）において、アニールしてＴｉとＳｉの固相
反応により高融点シリサイド層としてＴｉ５ｉｚ １１
（６＾−Ｇ）、（６Ａ−５）、（６Ａ−Ｄ）を形成し、
ＳｉＯ□サイドウオール５上のＴｉは選択エツチング法
により除去する。In FIG. 2 (4), Ti5iz 11 is annealed and formed into a high melting point silicide layer by a solid phase reaction between Ti and Si.
(6^-G), (6A-5), (6A-D) are formed,
Ti on the SiO□ sidewall 5 is removed by selective etching.
以上により主要工程は終わる。With the above steps, the main process is completed.
図示していないが、この後ＣＶＤ法により基板全面に燐
珪酸ガラス（ＰＳＧ）層を被着し、ソース、ドレイン領
域のＴｉ５ｉｚ層（６Ａ−５）、（６Ａ−Ｄ）上に、ま
たはそのいずれかにコンタクト孔を開けてアルミニウム
（ＡＩ）電極を形成する。Although not shown, a phosphosilicate glass (PSG) layer is then deposited on the entire surface of the substrate by the CVD method, and a layer of phosphosilicate glass (PSG) is deposited on the Ti5iz layers (6A-5) and (6A-D) in the source and drain regions, or on either of them. A contact hole is made in the crab to form an aluminum (AI) electrode.
ゲート電極、およびソース、ドレイン領域上に固相反応
により高融点金属シリサイド層を形成する従来方法によ
ると、ゲート電極上とソース、ドレイン令頁域上の高融
点金属シリサイド層の層抵抗値をそれぞれ独立に制御す
ることはできなく、従ってゲート電極の高融点金属シリ
サイド層の層抵抗値を下げるためには、高融点金属シリ
サイド層形成のための高融点金属を厚く被着しなければ
ならず、大きなストレスを基板にあたえると云う欠点が
ある。According to the conventional method of forming a high melting point metal silicide layer on the gate electrode, source and drain regions by solid phase reaction, the layer resistance values of the high melting point metal silicide layer on the gate electrode and the source and drain regions are respectively Therefore, in order to lower the layer resistance value of the high melting point metal silicide layer of the gate electrode, the high melting point metal for forming the high melting point metal silicide layer must be deposited thickly. The drawback is that it applies a large amount of stress to the board.
上記問題点の解決は、半導体基板（１）上のゲート形成
領域に高融点金属シリサイド層（４）を形成し、該高融
点金属シリサイド層（４）上、および半導体基板（１１
上に高融点金属Ｎ（６）を形成し、加熱により液高融点
金属層（６）を高融点金属シリサイド層（６Ａ−Ｇ）、
（６Ａ−Ｓ）、（６Ａ−Ｄ）に変換する工程を含む本発
明による半導体装置の製造方法により達成される。The above problem can be solved by forming a high melting point metal silicide layer (4) in the gate formation region on the semiconductor substrate (1), and forming a high melting point metal silicide layer (4) on the semiconductor substrate (11).
A high melting point metal N (6) is formed on top, and by heating, the liquid high melting point metal layer (6) is formed into a high melting point metal silicide layer (6A-G),
This is achieved by the method for manufacturing a semiconductor device according to the present invention, which includes the steps of converting into (6A-S) and (6A-D).
本発明はゲート電極とソース、ドレイン領域上の高融点
金属シリサイド層の層抵抗値をそれぞれ独立に制御する
ために、低抵抗値が要求されるゲート電極上にあらかじ
め高融点金属シリサイド層を敷いておき、その上に従来
と同程度の厚さの高融点金属層を被着し、固相反応によ
り高融点金属シリサイド層に変換するものである。In the present invention, in order to independently control the layer resistance values of the high melting point metal silicide layers on the gate electrode, source and drain regions, a high melting point metal silicide layer is laid in advance on the gate electrode where a low resistance value is required. Then, a high melting point metal layer with the same thickness as the conventional method is deposited thereon, and the layer is converted into a high melting point metal silicide layer by a solid phase reaction.
このようにすれば、従来と同程度の厚さの高融点金属層
の被着でよく、従って基板のストレス発生を防止し、か
つゲート電極の抵抗を下げ、デバイスの高速化を可能と
する。In this way, it is sufficient to deposit a high melting point metal layer with the same thickness as in the conventional method, thereby preventing the occurrence of stress on the substrate, lowering the resistance of the gate electrode, and making it possible to increase the speed of the device.
第１図（１）〜（４）はゲート電極、およびソース、ド
レイン領域上に高融点金属シリサイド層を形成する本発
明による方法を工程順に説明する断面図である。FIGS. 1(1) to 1(4) are cross-sectional views illustrating the method of forming a refractory metal silicide layer on a gate electrode and source and drain regions in the order of steps according to the present invention.
第１図（１１において、■は半導体基板、例えばｐ−５
ｉ基板で、この上に熱酸化により厚さ２００〜５００人
のゲート酸化膜２、ＣＶＤ法により厚さ２０００人のポ
リＳｉ層３、スパッタ法により高融点金属シリサイド層
として厚さ１０００人のＴｉ５ｉｚ層４を１傾次ｖｊ、
着し、通常のフォトプロセスを用いてこれらの層をパタ
ーニングしてゲート電極を形成する。Figure 1 (in 11, ■ is a semiconductor substrate, e.g. p-5
On this substrate, a gate oxide film 2 of 200 to 500 nm thick is formed by thermal oxidation, a poly-Si layer 3 of 2000 nm thick is formed by CVD, and a Ti5iz layer of 1000 nm thick is formed as a refractory metal silicide layer by sputtering. Layer 4 has 1st degree vj,
These layers are then patterned to form gate electrodes using conventional photoprocessing.
つぎに、ゲート電極をマスクにして、イオン注入により
ｎ“型のソース、ドレイン領域１１．１２を形成する。Next, using the gate electrode as a mask, n" type source and drain regions 11 and 12 are formed by ion implantation.
第１図（２）において、ＣＶＤ法により、ゲート電極を
覆って基板上全面に厚さ２０００〜４０００人のＳｉ０
２層を被着し、ＲＩＥ法による垂直方向に優勢な異方性
エツチングを用いてＳｉＯ□サイドウオール５を形成す
る。In FIG. 1 (2), a Si0 layer with a thickness of 2000 to 4000 layers is deposited over the entire surface of the substrate, covering the gate electrode, by the CVD method.
Two layers are deposited and a SiO□ sidewall 5 is formed using vertically dominant anisotropic etching by RIE.
第１図（３）において、スパッタ法により、基板全面に
高融点金属層として厚さ３００人のＴｉ層６を被着する
。In FIG. 1(3), a Ti layer 6 having a thickness of 300 nm is deposited as a high melting point metal layer over the entire surface of the substrate by sputtering.
第１図（４）において、アニールしてＴｉとＳｉの固相
反応により高融点シリサイド層としてＴｉ５ｉｚ Ｎ（
６Ａ−Ｇ）、（６Ａ−５）、（６Ａ−Ｄンを形成し、５
ｉｎ２サイドウオール５上のＴｉはエツチングにより除
去する。In FIG. 1 (4), Ti5iz N(
6A-G), (6A-5), (6A-D), 5
Ti on the in2 sidewall 5 is removed by etching.
アニール、およびエツチング条件は次のとおりである。The annealing and etching conditions are as follows.
まず、６５０〜７００°Ｃでプレアニールして、ポリＳ
ｉ層３、およびＳｉ基板１上のＴｉをＴｉ５ｉｚに変換
し、過酸化水素（＋１２０□）と水酸化アンモニウム
（ＮＨ４０１υを水で希釈した液でエツチングして
、 ５ｉＯｔサイドウオール５上のＴｉを除去する。First, pre-anneal at 650-700°C to make polyS
Convert Ti on the i-layer 3 and Si substrate 1 to Ti5iz, and add hydrogen peroxide (+120□) and ammonium hydroxide.
(Ti on the 5iOt sidewall 5 is removed by etching with a diluted solution of NH401υ with water.
つぎに、約８００℃でアニールを行う。Next, annealing is performed at about 800°C.
以上により主要工程は終わる。With the above steps, the main process is completed.
図示していないが、この後ＣＶＤ法により基板全面にＰ
ＳＧ層を被着し、ソース、ドレイン領域のＴｉＳｉ２層
（６Ａ−５）、（６Ａ−Ｄ）上に、またはそのいずれか
にコンタクト孔を開けてＡＩ電極を形成する。Although not shown, P is then applied to the entire surface of the substrate using the CVD method.
A SG layer is deposited, and contact holes are formed on or on the TiSi2 layers (6A-5) and (6A-D) in the source and drain regions to form AI electrodes.
実施例においては、高融点金属層としてＴｉを用いたが
、これの代わりに他の高融点金属層、例えばタングステ
ン（−）を用いてもよい。In the embodiment, Ti was used as the high melting point metal layer, but other high melting point metal layers, such as tungsten (-), may be used instead.
以上詳細に説明したように本発明によれば、ゲート電極
、およびソース、ドレイン領域上に高融点金属シリサイ
ド層を形成する際、ゲート電極とソース、ドレイン領域
上の高融点金属シリサイド層の層抵抗値をそれぞれ独立
に制御することができるため、基板にストレスをあたえ
ないで、またゲートとソース、ドレインがショートしな
い厚さで高融点金属シリサイド層形成のための高融点金
属を被着でき、かつゲート電極の抵抗を下げ、高速デバ
イスが得られる。As described in detail above, according to the present invention, when forming a high melting point metal silicide layer on the gate electrode, source, and drain regions, the layer resistance of the high melting point metal silicide layer on the gate electrode, source, and drain regions is Since the values can be controlled independently, it is possible to deposit the refractory metal for forming a refractory metal silicide layer without applying stress to the substrate, and at a thickness that does not short-circuit the gate, source, and drain. By lowering the resistance of the gate electrode, a high-speed device can be obtained.
第１図（１）〜（４）はゲート電極、およびソース、ド
レイン領域上に高融点金属シリサイド層を形成する本発
明による方法を工程順に説明する断面図、第２図（１１
〜（４）はゲー（・電極、およびソース、ドレイン領域
上に高融点金属シリサイド層を形成する従来例による方
法を工程順に説明する断面図である。
図において、
１は半導体基板で、例えばｐ−３ｉ基板、１１．１２は
ソース、ドレイン領域、
２はゲート酸化膜、
３はポリＳｉ層、
４は高融点金属シリサイド層でＴｉ５ｉｚ層、５はＳｉ
Ｏ□サイドウオール、
６は高融点金属層でＴｉ層、
６Ａ−Ｇ、６Ａ−３，６Ａ−Ｄは高融点シリサイド層で
Ｔｉ５ｉｚ層
不発明の１１呈を３０月する断曲図
第 １ 図
従来工牙呈ｔ−説明する曲゛面回
第２図Figures 1 (1) to (4) are cross-sectional views illustrating the method according to the present invention for forming a refractory metal silicide layer on the gate electrode, source and drain regions in order of process, and Figure 2 (11)
-(4) are cross-sectional views illustrating, in order of steps, a conventional method for forming a high melting point metal silicide layer on gate electrodes and source and drain regions. In the figures, 1 is a semiconductor substrate, for example -3i substrate, 11.12 is source and drain region, 2 is gate oxide film, 3 is poly-Si layer, 4 is high melting point metal silicide layer, Ti5iz layer, 5 is Si
O □ sidewall, 6 is a high melting point metal layer, Ti layer, 6A-G, 6A-3, 6A-D are high melting point silicide layers, Ti5iz layer. Fig. 2
Claims (1)
サイド層（４）を形成し、 該高融点金属シリサイド層（４）上、および半導体基板
（１）上に高融点金属層（６）を形成し、加熱により該
高融点金属層（６）を高融点金属シリサイド層（６Ａ−
Ｇ）、（６Ａ−Ｓ）、（６Ａ−Ｄ）に変換する工程を含
むことを特徴とする半導体装置の製造方法。[Claims] A high melting point metal silicide layer (4) is formed in a gate formation region on a semiconductor substrate (1), and a high melting point metal silicide layer (4) is formed on the high melting point metal silicide layer (4) and on the semiconductor substrate (1). A metal layer (6) is formed and heated to convert the high melting point metal layer (6) into a high melting point metal silicide layer (6A-
G), (6A-S), and (6A-D).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20752085A JPS6266679A (en) | 1985-09-19 | 1985-09-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20752085A JPS6266679A (en) | 1985-09-19 | 1985-09-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6266679A true JPS6266679A (en) | 1987-03-26 |
Family
ID=16541079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20752085A Pending JPS6266679A (en) | 1985-09-19 | 1985-09-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6266679A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01314709A (en) * | 1988-06-09 | 1989-12-19 | Katsuichiro Sato | Swimming wear with waterproof pocket |
| JPH04342141A (en) * | 1991-05-17 | 1992-11-27 | Mitsubishi Electric Corp | Manufacture of mos transistor |
| KR100334866B1 (en) * | 1998-12-28 | 2002-10-25 | 주식회사 하이닉스반도체 | Transistor Formation Method of Semiconductor Device |
| US6869867B2 (en) | 1997-10-01 | 2005-03-22 | Kabushiki Kaisha Toshiba | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same wherein the silicide on gate is thicker than on source-drain |
| JP2008500728A (en) * | 2004-05-26 | 2008-01-10 | フリースケール セミコンダクター インコーポレイテッド | Manufacturing method of semiconductor device having silicide layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5799775A (en) * | 1980-12-12 | 1982-06-21 | Toshiba Corp | Manufacture of semiconductor device |
| JPS624371A (en) * | 1985-06-28 | 1987-01-10 | ノ−ザン・テレコム・リミテツド | Manufacture of vlsi circuit using heat resistant metal silicide |
-
1985
- 1985-09-19 JP JP20752085A patent/JPS6266679A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5799775A (en) * | 1980-12-12 | 1982-06-21 | Toshiba Corp | Manufacture of semiconductor device |
| JPS624371A (en) * | 1985-06-28 | 1987-01-10 | ノ−ザン・テレコム・リミテツド | Manufacture of vlsi circuit using heat resistant metal silicide |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01314709A (en) * | 1988-06-09 | 1989-12-19 | Katsuichiro Sato | Swimming wear with waterproof pocket |
| JPH04342141A (en) * | 1991-05-17 | 1992-11-27 | Mitsubishi Electric Corp | Manufacture of mos transistor |
| US6869867B2 (en) | 1997-10-01 | 2005-03-22 | Kabushiki Kaisha Toshiba | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same wherein the silicide on gate is thicker than on source-drain |
| US7220672B2 (en) | 1997-10-01 | 2007-05-22 | Kabushiki Kaisha Toshiba | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same |
| US7638432B2 (en) | 1997-10-01 | 2009-12-29 | Kabushiki Kaisha Toshiba | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same |
| KR100334866B1 (en) * | 1998-12-28 | 2002-10-25 | 주식회사 하이닉스반도체 | Transistor Formation Method of Semiconductor Device |
| JP2008500728A (en) * | 2004-05-26 | 2008-01-10 | フリースケール セミコンダクター インコーポレイテッド | Manufacturing method of semiconductor device having silicide layer |
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