KR100315028B1 - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR100315028B1
KR100315028B1 KR1019980059151A KR19980059151A KR100315028B1 KR 100315028 B1 KR100315028 B1 KR 100315028B1 KR 1019980059151 A KR1019980059151 A KR 1019980059151A KR 19980059151 A KR19980059151 A KR 19980059151A KR 100315028 B1 KR100315028 B1 KR 100315028B1
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film
film pattern
forming
interlayer insulating
photoresist film
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KR1019980059151A
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Korean (ko)
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KR20000042859A (en
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이태국
최상태
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 한번의 마스크 공정을 이용한 비교적 단순한 공정으로 새로운 데머신 공정을 진행하여 배선 사이의 브리지를 방지함과 더불어 제조비용을 감소시킬 수 있는 반도체 소자의 금속 배선 형성방법을 제공한다.The present invention provides a method of forming a metal wiring of a semiconductor device which can reduce the manufacturing cost and prevent the bridge between wirings by performing a new demachine process in a relatively simple process using a single mask process.

본 발명에 따른 반도체 소자의 금속 배선 형성방법은 반도체 소자의 금속 배선 형성방법은 반도체 기판 상에 층간절연막을 형성하는 단계; 층간절연막 상에 콘택을 구비한 배선형태의 개구부를 갖는 포토레지스트막 패턴을 형성하는 단계; 개구부로 노출된 층간절연막을 소정 깊이만큼 식각하여 트렌치를 형성하는 단계; 포토레지스트막 패턴이 형성된 기판 전면에 상기 트렌치에 매립되도록 리럭스막을 형성하는 단계; 리럭스막을 포토레지스트막 패턴과 반응시켜 포토레지스트막 패턴 주위에 흡착된 리럭스막 패턴을 형성하여 트렌치를 노출시키는 단계; 리럭스막 패턴 및 포토레지스트막 패턴을 식각 마스크로하여 트렌치를 식각하여 배선형태의 콘택홀을 형성하는 단계; 리럭스막 패턴 및 포토레지스트막 패턴을 제거하는 단계; 콘택홀에 매립되도록 층간절연막 상에 배선용 금속막을 형성하는 단계; 및, 금속막을 층간절연막이 노출될 때까지 전면식각하여 금속배선을 형성하는 단계를 포함한다.Method for forming a metal wiring of a semiconductor device according to the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate; Forming a photoresist film pattern having an opening in a wiring form having a contact on the interlayer insulating film; Etching the interlayer insulating film exposed through the opening to a predetermined depth to form a trench; Forming a reduction film on the entire surface of the substrate on which the photoresist film pattern is formed so as to fill the trench; Reacting the deluxe film with the photoresist film pattern to form a desorbed film pattern adsorbed around the photoresist film pattern to expose the trench; Etching the trench using the reduction film pattern and the photoresist film pattern as an etching mask to form a contact hole in a wiring form; Removing the relux film pattern and the photoresist film pattern; Forming a wiring metal film on the interlayer insulating film so as to be buried in the contact hole; And etching the entire surface of the metal film until the interlayer insulating film is exposed to form the metal wiring.

Description

반도체 소자의 금속 배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히 이중 데머신(dual damascene) 공정에 의한 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices by a dual damascene process.

반도체 디바이스의 고집적화에 따라, 배선 설계가 자유롭고 용이하며, 배선 저항 및 전류용량 등의 설정을 여유있게 할 수 있는 배선 기술에 관한 연구가 활발히 진행되고 있다.BACKGROUND ART With the high integration of semiconductor devices, research on wiring technology that allows free and easy wiring design and allows setting of wiring resistance and current capacity, etc., has been actively conducted.

도 1은 종래의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도이다. 도 1을 참조하면, 반도체 기판(10) 상에 층간절연막(11)을 형성하고, 기판(10)일부가 노출되도록 층간절연막(11)을 식각하여 콘택홀을 형성한다. 상기 콘택홀에 매립되도록 층간절연막(11) 상에 금속막을 증착하고 패터닝하여 금속 배선(12a, 12b)을 형성한다.1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device. Referring to FIG. 1, an interlayer insulating layer 11 is formed on a semiconductor substrate 10, and a contact hole is formed by etching the interlayer insulating layer 11 to expose a portion of the substrate 10. Metal wires 12a and 12b are formed by depositing and patterning a metal film on the interlayer insulating film 11 so as to be filled in the contact hole.

그러나, 상기한 바와 같이 양각 공정에 의해 배선을 형성하는데, 금속막의 열악한 식각 특성에 의해, 도 1에 도시된 바와 같이, 식각 후 금속 배선(12a, 12b) 사이에서 브리지가 발생된다. 이러한, 브리지는 소자의 고집적화에 따라 더욱더 심해져서 소자의 전기적 특성을 저하시킨다.However, as described above, the wiring is formed by an embossing process, and due to the poor etching characteristics of the metal film, as shown in FIG. 1, a bridge is generated between the metal wirings 12a and 12b after etching. Such bridges become more severe with high integration of the device, thereby degrading the electrical characteristics of the device.

따라서, 종래에는 고집적화에 따른 배선 사이의 브리지를 방지하기 위하여 데머신(damascene) 공정으로 배선을 형성하였다. 즉, 도 2는 데머신 공정에 의해 형성된 반도체 소자의 금속 배선을 나타낸 단면도로서, 도 1에서와는 달리 층간절연막(21) 내에 화학기계연마(Chemical Mechanical Polishing; CMP)로 금속막을 전면 식각하여 금속 배선(22)을 완전히 매립시켜 형성하기 때문에, 금속막의 열악한식각특성으로 인해 발생되는 인접 배선과의 브리지 문제가 방지된다.Therefore, in the related art, wirings were formed by a damascene process to prevent bridges between wirings due to high integration. That is, FIG. 2 is a cross-sectional view illustrating a metal wiring of a semiconductor device formed by a demachine process. Unlike FIG. 1, the metal film is etched by chemical mechanical polishing (CMP) in the interlayer insulating film 21. Since 22) is completely embedded, the bridge problem with the adjacent wiring caused by the poor etching characteristics of the metal film is prevented.

그러나, 상기한 데머신 공정에 의한 금속배선을 형성하는데 있어서는, 도 1에서와는 달리 금속 배선(22)의 형태로 콘택홀을 형성해야 하기 때문에, 2번의 마스크 공정, 예컨대 2번의 포토레지스트막의 도포, 노광 및 현상공정이 요구될 뿐만 아니라 2번의 식각공정이 각각 진행되어야 한다. 이에 따라, 공정이 복잡해지고, 제조비용이 높아지는 문제가 발생한다.However, in forming the metal wiring by the above-described demachine process, since the contact hole must be formed in the form of the metal wiring 22 unlike in FIG. 1, two mask processes, for example, application and exposure of two photoresist films are performed. In addition to the development and development process, two etching processes must be performed respectively. As a result, the process becomes complicated and the production cost increases.

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 한번의마스크 공정을 이용한 비교적 단순한 공정으로 새로운 데머신 공정을 진행하여 배선 사이의 브리지를 방지함과 더불어 제조비용을 감소시킬 수 있는 반도체 소자의 금속 배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, a semiconductor that can reduce the manufacturing cost and prevent the bridge between the wiring by performing a new demachine process in a relatively simple process using a single mask process It is an object of the present invention to provide a method for forming a metal wiring of an element.

도 1은 종래의 반도체 소자의 금속 배선을 나타낸 단면도.1 is a cross-sectional view showing a metal wiring of a conventional semiconductor device.

도 2는 종래의 데머신 공정에 의한 반도체 소자의 금속 배선을 나타낸 단면도.2 is a cross-sectional view showing a metal wiring of a semiconductor device by a conventional demachine process.

도 3a 내지 도 3j는 본 발명의 실시예에 따른 데머신 공정에 의한 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도.3A to 3J are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device by a demachine process according to an embodiment of the present invention.

도 4는 포토레지스트막 패턴을 나타낸 평면도.4 is a plan view showing a photoresist film pattern.

도 5는 열처리후 리럭스막 패턴을 나타낸 평면도5 is a plan view showing a relux film pattern after heat treatment

〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]

30 : 반도체 기판 31 : 층간절연막30 semiconductor substrate 31 interlayer insulating film

32 : 포토레지스트막 패턴 33 : 트렌치32 photoresist film pattern 33 trench

34 : 리럭스막 34A : 리럭스막 패턴34: Lux film 34A: Lux film pattern

35 : 콘택홀 36 : 금속막35 contact hole 36 metal film

36A : 금속배선36A: Metal Wiring

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성방법은 반도체 기판 상에 층간절연막을 형성하는 단계; 층간절연막 상에 콘택을 구비한 배선형태의 개구부를 갖는 포토레지스트막 패턴을 형성하는 단계; 개구부로 노출된 층간절연막을 소정 깊이만큼 식각하여 트렌치를 형성하는 단계; 포토레지스트막 패턴이 형성된 기판 전면에 상기 트렌치에 매립되도록 리럭스막을 형성하는 단계; 리럭스막을 포토레지스트막 패턴과 반응시켜 포토레지스트막 패턴 주위에 흡착된 리럭스막 패턴을 형성하여 트렌치를 노출시키는 단계; 리럭스막 패턴 및 포토레지스트막 패턴을 식각 마스크로하여 트렌치를 식각하여 배선형태의 콘택홀을 형성하는 단계; 리럭스막 패턴 및 포토레지스트막 패턴을 제거하는 단계; 콘택홀에 매립되도록 층간절연막 상에 배선용 금속막을 형성하는 단계; 및, 금속막을 층간절연막이 노출될 때까지 전면식각하여 금속배선을 형성하는 단계를 포함한다.Method of forming a metal wiring of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate; Forming a photoresist film pattern having an opening in a wiring form having a contact on the interlayer insulating film; Etching the interlayer insulating film exposed through the opening to a predetermined depth to form a trench; Forming a reduction film on the entire surface of the substrate on which the photoresist film pattern is formed so as to fill the trench; Reacting the deluxe film with the photoresist film pattern to form a desorbed film pattern adsorbed around the photoresist film pattern to expose the trench; Etching the trench using the reduction film pattern and the photoresist film pattern as an etching mask to form a contact hole in a wiring form; Removing the relux film pattern and the photoresist film pattern; Forming a wiring metal film on the interlayer insulating film so as to be buried in the contact hole; And etching the entire surface of the metal film until the interlayer insulating film is exposed to form the metal wiring.

또한, 층간절연막은 고밀도 플라즈마 산화막으로 형성하고, 포토레지스트막 패턴은 층간절연막 상에 포토레지스트막을 도포하고, 콘택용 레티클과 배선용 레티클을 이용하여 노광한 후, 현상하여 형성한다.The interlayer insulating film is formed of a high density plasma oxide film, and the photoresist film pattern is formed by applying a photoresist film on the interlayer insulating film, exposing using a contact reticle and a wiring reticle, and then developing.

또한, 리럭스막과 포토레지스트막 패턴의 반응은 열처리로 진행한다.In addition, the reaction between the reduction film and the photoresist film pattern is performed by heat treatment.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 3a 내지 도 3j는 본 발명의 실시예에 따른 새로운 데머신 공정에 의한 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.3A to 3J are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device by a new demachine process according to an embodiment of the present invention.

도 3a에 도시된 바와 같이, 반도체 기판(30) 상에 층간절연막(31)을 형성한다. 층간절연막(31)은 고밀도 플라즈마(High Density Plasma; HDP) 산화막으로 형성한다. 그런 다음, 층간절연막(31) 상에 포토레지스트막을 도포하고, 콘택홀용 레티클과 배선용 레티클을 동시에 이용하여 포토레지스트막을 노광한 후 현상하여, 도 3b에 도시된 바와 같이, 콘택을 구비한 배선형태로 층간절연막(31)을 노출시키는 포토레지스트막 패턴(32)을 형성한다. 즉, 포토레지스트막 패턴(32)은 도 4에 도시된 바와 같이, 콘택부분 및 배선형태의 개구부를 갖는다.As shown in FIG. 3A, an interlayer insulating film 31 is formed on the semiconductor substrate 30. The interlayer insulating film 31 is formed of a high density plasma (HDP) oxide film. Then, a photoresist film is applied on the interlayer insulating film 31, and the photoresist film is exposed and developed by using a contact hole reticle and a wiring reticle at the same time, and as shown in FIG. 3B, in the form of a wiring having a contact. A photoresist film pattern 32 exposing the interlayer insulating film 31 is formed. That is, the photoresist film pattern 32 has a contact portion and an opening in the form of a wiring as shown in FIG.

도 3c를 참조하면, 포토레지스트막 패턴(32)을 식각 마스크로하여, 노출된 층간절연막(31)을 소정 깊이만큼 식각하여 트렌치(33)를 형성한다. 이때, 식각은 건식식각으로 진행한다. 그런 다음, 도 3d에 도시된 바와 같이, 포토레지스트막 패턴(32)이 형성된 기판 전면에 트렌치(33)에 매립되도록 리럭스(RELUX)막(34)를 도포한다. 리럭스는 열 또는 빛에 의해 포토레지스트와 반응하는 물질로서, 포토레지스트와 접촉된 부분에서만 반응이 진행되어 반응후에는 포토레지스트막 주위에 흡착된 형태로 패턴이 변형된다. 본 실시예에서는 리럭스막(34)을 포토레지스트막 패턴(32)과 반응시키기 위하여, 베이킹과 같은 열처리 공정을 진행한 후 DI로 세정한다. 이때, 포토레지스트막 패턴(32)과 접촉된 부분에서만 반응이 진행되어, 도 3e에 도시된 바와같이, 포토레지스트막 패턴(32) 주변에 흡착된 형태의 리럭스막 패턴(34A)으로 변형되어 트렌치(33)를 노출시킨다. 한편, 열처리후 변형된 리럭스막 패턴(34A)을 평면에서 살펴보면, 도 5에 도시된 바와 같이, 콘택부분에서만 트렌치 (33)가 노출되게 된다. 즉, 리럭스막 패턴(34A)에 의해, 콘택부분의 CD(Critical Dimension)이 조절될 수 있다. 또한, 리럭스와 포토레지스트의 반응을 촉진시키기 위하여, 열처리전에 포토레지스트막 패턴(32) 표면을 산처리한다.Referring to FIG. 3C, the trench 33 is formed by etching the exposed interlayer insulating layer 31 by a predetermined depth using the photoresist layer pattern 32 as an etching mask. At this time, the etching proceeds to dry etching. Then, as shown in FIG. 3D, a RELUX film 34 is applied to the entire surface of the substrate on which the photoresist film pattern 32 is formed so as to be embedded in the trench 33. Relux is a material that reacts with the photoresist by heat or light, and the reaction proceeds only at the portion in contact with the photoresist, and after the reaction, the pattern is deformed to be adsorbed around the photoresist film. In the present embodiment, in order to react the reduction film 34 with the photoresist film pattern 32, a heat treatment process such as baking is performed, followed by washing with DI. At this time, the reaction proceeds only at the portion in contact with the photoresist film pattern 32, and as shown in FIG. 3E, the reaction film is deformed into the form of the relux film pattern 34A adsorbed around the photoresist film pattern 32. The trench 33 is exposed. On the other hand, when the plan view of the deluxe film pattern 34A deformed after the heat treatment, as shown in Figure 5, the trench 33 is exposed only in the contact portion. That is, the CD (Critical Dimension) of the contact portion may be adjusted by the Lux film pattern 34A. Further, in order to promote the reaction between the relux and the photoresist, the surface of the photoresist film pattern 32 is acid treated before heat treatment.

그리고 나서, 포토레지스트막 패턴(32)과 리럭스막 패턴(34A)을 식각 마스크로하여 노출된 트렌치(33)를 건식식각한다. 이때, 식각플로우가 도 3f에 도시된 바와 같이, 리럭스막 패턴(34A)의 하부의 트렌치(33) 내에서 상하로 진행되어, 도 3g에 도시된 바와 같이 경사진 측벽을 갖는 배선 형태의 콘택홀(35)이 형성된다. 즉, 별도의 습식식각의 진행없이 건식식각만으로 콘택홀(35)의 스텝 커버리지가 개선된다. 그런 다음, 도 3h에 도시된 바와 같이, 리럭스막 패턴(34A)과 포토레지스트막 패턴(32)을 제거하고, 도 3i에 도시된 바와 같이, 콘택홀(35)에 매립되도록 층간절연막(31) 상에 배선용 금속막(36)을 형성한다. 그 후, 금속막(36)을 층간절연막(31)이 노출될 때까지 전면식각하여, 도 3j에 도시된 바와 같이, 층간절연막(31)내에 완전히 매립된 형태로 배선(36A)을 형성한다. 이때, 전면식각은 화학기계연마 (Chemical Mechanical Polishing; CMP) 기술로 진행한다.Thereafter, the exposed trench 33 is dry-etched using the photoresist film pattern 32 and the reduction film pattern 34A as an etching mask. At this time, as shown in FIG. 3F, the etching flow proceeds up and down in the trench 33 in the lower portion of the reduction film pattern 34A to form a wire-type contact having an inclined sidewall as shown in FIG. 3G. The hole 35 is formed. That is, the step coverage of the contact hole 35 may be improved only by dry etching without additional wet etching. Then, as shown in FIG. 3H, the interlayer insulating film 31 is removed to fill the contact hole 35 as shown in FIG. 3I by removing the reduction film pattern 34A and the photoresist film pattern 32. A wiring metal film 36 is formed. Thereafter, the metal film 36 is etched entirely until the interlayer insulating film 31 is exposed, thereby forming the wiring 36A in a form completely embedded in the interlayer insulating film 31, as shown in FIG. 3J. At this time, the front etching is performed by chemical mechanical polishing (CMP) technology.

상기한 본 발명에 의하면, 데머신 공정에 의한 배선의 형성시, 한번의 노광공정 및 현상공정으로 배선형태의 포토레지스트막 패턴을 형성하고, 포토레지스트와 반응하는 리럭스 물질을 이용하여 배선의 CD(Critical Dimension)를 조절하여 콘택홀을 형성한다. 이에 따라, 데머신 공정에 의해 배선 사이의 브리지 문제가 방지되면서, 공정이 단순해질 뿐만 아니라, 콘택홀의 CD 조정이 용이해진다. 또한, 배선형태의 콘택홀 형성시, 포토레지스트막 패턴과 리럭스막 패턴을 식각 마스크로서 모두 이용하기 때문에, 건식식각만으로도 콘택홀의 스텝 커버리지가 개선되어, 금속막을 용이하게 증착할 수 있는 효과가 있다.According to the present invention described above, in the formation of the wiring by the demachine process, a photoresist film pattern in the form of wiring is formed in one exposure step and the developing step, and the CD of the wiring is made by using a reflex material reacting with the photoresist. Adjust the (Critical Dimension) to form a contact hole. Accordingly, while the bridge problem between wirings is prevented by the demachine process, not only the process is simplified but also CD adjustment of the contact hole is easy. In addition, since both the photoresist film pattern and the reduction film pattern are used as an etch mask when forming a contact hole in the form of a wiring, the step coverage of the contact hole is improved only by dry etching, so that a metal film can be easily deposited. .

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (9)

반도체 기판 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate; 상기 층간절연막 상에 콘택을 구비한 배선형태의 개구부를 갖는 포토레지스트막 패턴을 형성하는 단계;Forming a photoresist film pattern on the interlayer insulating film, the photoresist film pattern having an opening in a wiring form having a contact; 상기 개구부로 노출된 층간절연막을 소정 깊이만큼 식각하여 트렌치를 형성하는 단계;Etching the interlayer insulating layer exposed through the opening to a predetermined depth to form a trench; 상기 포토레지스트막 패턴이 형성된 기판 전면에 상기 트렌치에 매립되도록 리럭스막을 형성하는 단계;Forming a reduction film on the entire surface of the substrate on which the photoresist film pattern is formed so as to fill the trench; 상기 리럭스막을 상기 포토레지스트막 패턴과 반응시켜 상기 포토레지스트막 패턴 주위에 흡착된 리럭스막 패턴을 형성하여 상기 트렌치를 노출시키는 단계;Reacting the deluxe film with the photoresist film pattern to form a deluxe film pattern adsorbed around the photoresist film pattern to expose the trench; 상기 리럭스막 패턴 및 포토레지스트막 패턴을 식각 마스크로하여 상기 트렌치를 식각하여 배선형태의 콘택홀을 형성하는 단계;Etching the trench using the recess film pattern and the photoresist film pattern as an etching mask to form a contact hole in a wiring form; 상기 리럭스막 패턴 및 포토레지스트막 패턴을 제거하는 단계;Removing the relux film pattern and the photoresist film pattern; 상기 콘택홀에 매립되도록 상기 층간절연막 상에 배선용 금속막을 형성하는 단계; 및,Forming a wiring metal film on the interlayer insulating film so as to fill the contact hole; And, 상기 금속막을 상기 층간절연막이 노출될 때까지 전면식각하여 금속배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Forming a metal wiring by etching the metal film on the entire surface until the interlayer insulating film is exposed. 제 1 항에 있어서, 상기 층간절연막은 고밀도 플라즈마 산화막으로 형성하는것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the interlayer insulating film is formed of a high density plasma oxide film. 제 1 항에 있어서, 상기 포토레지스트막 패턴을 형성하는 단계는The method of claim 1, wherein the forming of the photoresist film pattern is performed. 상기 층간절연막 상에 포토레지스트막을 도포하는 단계;Applying a photoresist film on the interlayer insulating film; 상기 포토레지스트막을 콘택용 레티클과 배선용 레티클을 이용하여 노광하는 단계; 및,Exposing the photoresist film using a contact reticle and a wiring reticle; And, 상기 노광된 포토레지스트막을 현상하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And developing the exposed photoresist film. 제 1 항에 있어서, 상기 트렌치를 형성하는 단계는 건식식각으로 진행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법,The method of claim 1, wherein the forming of the trench is performed by dry etching. 제 1 항에 있어서, 상기 리럭스막과 상기 포토레지스트막 패턴의 반응은 열처리로 진행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the reaction between the relux film and the photoresist film pattern is performed by heat treatment. 제 1 항에 있어서, 상기 콘택홀을 형성하는 단계는 건식식각만을 이용하여 진행하고, 상기 콘택홀은 측벽경사를 갖는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the forming of the contact hole is performed using only dry etching, and the contact hole has a sidewall inclination. 제 1 항에 있어서, 상기 리럭스막과 상기 포토레지스트막 패턴의 반응전에상기 포토레지스트막 패턴 표면을 산처리하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein an acid treatment of the surface of the photoresist film pattern is performed before the reaction of the relux film and the photoresist film pattern. 제 1 항에 있어서, 상기 리럭스막 패턴을 형성하는 단계에서 상기 반응후 미반응된 리럭스막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.2. The method of claim 1, further comprising removing an unreacted relux film after the reaction in forming the relux film pattern. 제 1 항에 있어서, 상기 전면식각은 화학기계연마기술로 진행하는 것을 특징으로 하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the front surface etching is performed by a chemical mechanical polishing technique.
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