KR100309809B1 - Method of forming a copper wiring in a semiconductor device - Google Patents
Method of forming a copper wiring in a semiconductor device Download PDFInfo
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- KR100309809B1 KR100309809B1 KR1019980059363A KR19980059363A KR100309809B1 KR 100309809 B1 KR100309809 B1 KR 100309809B1 KR 1019980059363 A KR1019980059363 A KR 1019980059363A KR 19980059363 A KR19980059363 A KR 19980059363A KR 100309809 B1 KR100309809 B1 KR 100309809B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Abstract
본 발명은 반도체 소자의 구리 금속 배선 형성 방법에 관한 것으로, 구리 시드층을 증착한 후, 진공파괴 없이 전기도금 증착을 하므로써, 기존의 전기도금전에 필수적으로 진행하던 프리-클리닝(pre-cleaning) 공정을 생략할 수 있을 뿐만 아니라, 물리기상증착법 또는 화학기상증착법으로 확산 방지막 및 구리 시드층을 형성하고, 전기도금법으로 구리층을 증착하고, 수소 환원 열처리를 실시하는 모든 공정을 진공파괴 없이 연속적으로 진행하므로써, 구리 금속 배선의 신뢰성, 안정성 및 성능을 향상시킬 있는 반도체 소자의 금속 배선 형성 방법에 관하여 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a copper metal wiring of a semiconductor device, and by depositing a copper seed layer and then performing electroplating deposition without vacuum destruction, a pre-cleaning process that is essential for conventional electroplating. In addition, all processes of forming a diffusion barrier film and a copper seed layer by physical vapor deposition or chemical vapor deposition, depositing a copper layer by electroplating, and performing hydrogen reduction heat treatment are continuously performed without vacuum destruction. Therefore, a method for forming a metal wiring of a semiconductor element that can improve the reliability, stability and performance of a copper metal wiring is described.
Description
본 발명은 반도체 소자의 구리 금속 배선 형성 방법에 관한 것으로, 특히 구리 금속 배선을 형성하기 위한 모든 공정을 진공파괴 없이 연속적으로 진행하여, 구리 금속 배선의 신뢰성, 안정성 및 성능을 향상시킬 있는 반도체 소자의 구리 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper metal wiring of a semiconductor device. In particular, all processes for forming a copper metal wiring are continuously performed without vacuum breaking, thereby improving the reliability, stability and performance of the copper metal wiring. A method of forming a copper metal wiring.
일반적으로, 반도체 소자 제조시 소자와 소자간 또는 배선과 배선간을 전기적으로 연결시키기 위해 금속 배선을 사용하고 있다. 금속 배선 재료로 알루미늄(Al) 또는 텅스텐(W)이 널리 사용되고 있으나, 낮은 융점과 높은 비저항으로 인하여 초고집적 반도체 소자에 더 이상 적용이 어렵게 되었다. 따라서, 차세대 반도체 소자의 초고집적화 및 고성능화를 실현하기 위해, 금속 배선의 대체 재료에 대한 개발 및 미세 선폭을 갖는 금속 배선의 형성에 대한 필요성이 대두되고 있는 실정이다. 대체 재료로 전도성이 우수한 물질인 구리(Cu), 금(Au), 은(Ag), 코발트(Co), 크롬(Cr), 니켈(Ni) 등이 있다. 이러한 물질들 중 비저항이 작고, 전자 이동(electromigration; EM)과 스트레스 이동(stress migration; SM) 등의 신뢰성이 우수하며, 생산원가가 저렴한 구리 및 구리 합금이 널리 적용되고 있는 추세이다.In general, in the manufacture of semiconductor devices, metal wires are used to electrically connect between devices and devices or between wires and wires. Although aluminum (Al) or tungsten (W) is widely used as a metal wiring material, its low melting point and high resistivity make it difficult to apply to ultra-high density semiconductor devices. Therefore, in order to realize ultra-high integration and high performance of next-generation semiconductor devices, there is a need for development of alternative materials for metal wiring and formation of metal wirings having a fine line width. Alternative materials include copper (Cu), gold (Au), silver (Ag), cobalt (Co), chromium (Cr), nickel (Ni), and the like. Among these materials, copper and copper alloys having low specific resistance, excellent reliability such as electromigration (EM) and stress migration (SM), and low production cost are widely applied.
즉, 차세대 반도체 소자의 초고집적화 및 급격한 고성능화로 인해 소자의 속도 향상 및 신뢰도 측면에서 관심이 고조되고 있으며, 이에 따라 구리를 이용한 금속 배선이 널리 적용되고 있는 추세이다. 구리 금속 배선은 현재 전기도금법을 이용한 방법 적용이 일반화되고 있는데, 전기도금법은 안정하고 깨끗한 구리 시드층(seed layer)의 증착이 필수적인 공정으로 되어 있다. 기존의 방법은 물리기상증착(PVD)법을 이용하기 위한 챔버 및 화학기상증착(CVD)법을 이용하기 위한 챔버로 구성된 장비에서 확산 방지막 및 구리 시드층을 증착한 후에 구리 전기도금 장비에서 구리 전기도금을 진행하고 있다. 이 경우, 구리 시드층 증착후 진공파괴 후에 전기도금을 진행하기 때문에 구리 시드층에 산화막이 형성되는 문제점을 가지고 있으며, 전기도금 장비에서 프리-클리닝(pre-cleaning)후 구리 전기도금이 진행되어 공정 단계가 늘어나 생산성을 저하시키는 요인이 된다.That is, due to the ultra-high integration and rapid high performance of the next-generation semiconductor device, interest in the speed improvement and reliability of the device is increasing, and accordingly, metal wiring using copper has been widely applied. The application of the method using the electroplating method is now common in copper metal wiring, and the electroplating method is a process in which deposition of a stable and clean copper seed layer is essential. Existing methods use copper electroplating equipment after depositing a diffusion barrier and copper seed layer in equipment consisting of a chamber for using physical vapor deposition (PVD) and a chamber for using chemical vapor deposition (CVD). Plating is in progress. In this case, since the electroplating is carried out after vacuum destruction after the deposition of the copper seed layer, an oxide film is formed on the copper seed layer, and copper electroplating is performed after pre-cleaning in the electroplating equipment. Increased levels are a factor in lowering productivity.
따라서, 본 발명은 구리층을 전기도금법으로 증착 하되, 구리 금속 배선을 형성하기 위한 모든 공정을 진공파괴 없이 연속적으로 진행하여, 구리 금속 배선의 신뢰성, 안정성 및 성능을 향상시킬 있는 반도체 소자의 구리 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to deposit the copper layer by the electroplating method, all the processes for forming the copper metal wiring without proceeding vacuum-breaking, thereby improving the reliability, stability and performance of the copper metal wiring copper metal of the semiconductor device It is an object to provide a wiring forming method.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 구리 금속 배선 형성 방법은 반도체 기판 상에 도전층 및 층간 절연막을 형성한 후 상기 층간 절연막의 소정 영역을 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 상기 층간 절연막 상에 확산 방지막을 형성하는 단계와, 상기 확산 방지막을 형성한 후 상기 확산 방지막을 형성하기 위한 장비와 구리 시드층을 형성하기 위한 장비의 압력을 동일하게 유지하여 진공파괴 없이 상기 확산 방지막 상에 구리 시드층을 형성하는 단계와, 상기 구리 시드층을 형성한 후에 상기 구리 시드층 형성 장비와 구리층 형성 장비의 압력을 동일하게 유지하여 진공파괴 없이 상기 구리 시드층상에 구리층을 형성하는 단계와, 상기 구리층을 형성한 후에 상기 구리층 형성 장비와 열처리 장비의 압력을 동이하게 유지하여 진공파괴 없이 상기 구리층을 수소환원 분위기에서 열처리하는 단계와, 상기 구리층을 패터닝하여 구리 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The method for forming a copper metal wiring of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a contact hole by forming a conductive layer and an interlayer insulating film on a semiconductor substrate and then etching a predetermined region of the interlayer insulating film; Forming a diffusion barrier on the interlayer insulating layer including the contact hole; and after forming the diffusion barrier, vacuum pressure is maintained by maintaining the pressure of equipment for forming the diffusion barrier and equipment for forming a copper seed layer. Forming a copper seed layer on the diffusion barrier layer without forming the copper seed layer, and after forming the copper seed layer, maintaining the pressure of the copper seed layer forming equipment and the copper layer forming equipment to be the same so that the copper on the copper seed layer without vacuum Forming a layer, and after forming the copper layer, the pressure of the copper layer forming equipment and heat treatment equipment To keep the copper characterized in that comprises a step of forming comprising the steps of: heat-treating the copper layer in a hydrogen reducing atmosphere, a copper metal wire by patterning the copper layer without breaking vacuum.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 구리 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of forming a copper metal wire in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 도전층11: semiconductor substrate 12: conductive layer
13: 층간 절연막 14: 콘택홀13: interlayer insulating film 14: contact hole
15: 확산 방지막 16: 구리 시드층15: diffusion barrier film 16: copper seed layer
17: 구리층17: copper layer
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 구리 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for explaining a method of forming a copper metal wire in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(11)에 도전층(12)을 형성하고, 도전층(12) 상에 층간 절연막(13)을 형성한다. 층간 절연막(13)의 일부분을 식각하여 도전층(12)이 노출되는 콘택홀(14)을 형성한다. 콘택홀(14)을 포함한 층간 절연막(13)이 형성된 기판을 확산 방지막 증착 챔버에 이송한 후 확산 방지막(15)을 형성한다.Referring to FIG. 1A, a conductive layer 12 is formed on a semiconductor substrate 11, and an interlayer insulating layer 13 is formed on the conductive layer 12. A portion of the interlayer insulating layer 13 is etched to form a contact hole 14 through which the conductive layer 12 is exposed. The substrate on which the interlayer insulating layer 13 including the contact hole 14 is formed is transferred to the diffusion barrier deposition chamber, and then the diffusion barrier 15 is formed.
상기에서, 도전층(12)은 불순물 이온 주입으로 반도체 기판(11)에 형성되는 접합부이거나, 전극 또는 하부 금속 배선 등 본 발명에 의해 형성될 금속 배선과 연결될 소자의 모든 구성 요소가 포함된다. 확산 방지막(15)은 일반적인 물리기상증착법이나 화학기상증착법을 이용하여 TiN, Ta, TaN, WNX, TiAl(N) 등을 10 내지 1000Å의 두께로 형성된다. 물리기상증착법은 -50℃∼200℃의 온도와 E-8∼E-9Torr의 고진공에서 실시하고, 화학기상증착법은 100℃∼400℃의 온도와 0.1∼10Torr의 압력에서 실시한다.In the above, the conductive layer 12 is a junction formed in the semiconductor substrate 11 by impurity ion implantation, or includes all components of an element to be connected to a metal wiring to be formed by the present invention, such as an electrode or a lower metal wiring. The diffusion barrier 15 is formed of TiN, Ta, TaN, WN X , TiAl (N), or the like by using a general physical vapor deposition method or chemical vapor deposition method with a thickness of 10 to 1000 kPa. Physical vapor deposition is carried out at a temperature of -50 ° C to 200 ° C and a high vacuum of E-8 to E-9 Torr, and chemical vapor deposition is carried out at a temperature of 100 ° C to 400 ° C and a pressure of 0.1 to 10 Torr.
도 1b를 참조하면, 확산 방지막(15)을 형성한 후에 확산 방지막 증착 챔버와 구리 시드층 증착 챔버의 진공도를 동일하게 유지하여 진공파괴 없이 확산 방지막(15) 상에 물리기상증착법이나 화학기상증착법으로 구리를 10 내지 1000Å의 두께로 증착하여 구리 시드층(16)을 형성한다.Referring to FIG. 1B, after the diffusion barrier 15 is formed, the vacuum barriers of the diffusion barrier deposition chamber and the copper seed layer deposition chamber are maintained at the same level, and physical vapor deposition or chemical vapor deposition is performed on the diffusion barrier 15 without vacuum destruction. Copper is deposited to a thickness of 10 to 1000 mm 3 to form a copper seed layer 16.
상기에서, 구리 시드층(16)을 물리기상증착법으로 형성할 경우, E-8∼E-9Torr의 고진공에서 실시하며, 증착 온도는 100 내지 500℃에서 실시한다. 한편, 구리 시드층(16)을 화학기상증착법으로 형성할 경우, 진공파괴를 방지하기 위해 E-3∼E-9Torr의 고진공 상태를 유지하도록 한다.In the above, when the copper seed layer 16 is formed by physical vapor deposition, it is carried out at a high vacuum of E-8 to E-9 Torr, and the deposition temperature is performed at 100 to 500 ° C. On the other hand, when the copper seed layer 16 is formed by chemical vapor deposition, the high vacuum state of E-3 to E-9 Torr is maintained to prevent vacuum destruction.
도 1c를 참조하면, 구리 시드층(16)을 형성한 후에 구리 시드층 증착 챔버와 구리층 증착 챔버의 진공도를 동일하게 유지하여 진공파괴 없이 구리 시드층(16) 상에 금속-유기 화학기상증착(MOCVD)법이나 전기도금법으로 구리를 증착하여 구리층(17)을 형성한다.Referring to FIG. 1C, after forming the copper seed layer 16, the vacuum degrees of the copper seed layer deposition chamber and the copper layer deposition chamber are maintained at the same, so that metal-organic chemical vapor deposition on the copper seed layer 16 is performed without vacuum destruction. The copper layer 17 is formed by depositing copper by the (MOCVD) method or the electroplating method.
상기에서, 금속-유기 화학기상증착법으로 구리층(17)을 증착할 경우, 증착 온도는 50 내지 300℃로 하며, 전구체(precursor)를 5 내지 100sccm(standard cubic centimeter per minute) 사용한다. 전구체로는 (hfac)CuTMVS 및 0.1∼20%의 TMVS, 0.1∼10%의 Hhfac, 0.1∼5% 1/2H20(hfac), 0.1~5%H20등이 첨가제가 포함된 상기 첨가제가 조합된 혼합체, (hfac)CuVTMOS 및 0.1∼20%의 VTMOS, 0.1∼10% Hhfac,0.1∼5% 1/2H20(hfac), 0.1∼5%H20등의 첨가제가 포함된 그 상기 첨가제가 조합된 혼합체, 그리고 (hfac)CuPENTENE 및 0.1∼20%의 PENTENE, 0.1∼10% Hhfac, 0.1∼5% 1/2H20(hfac), 0.1~5%H20등 첨가제가 포함된 상기 첨가제가 포함된 혼합체 중 어느 하나를 사용한다.In the above, in the case of depositing the copper layer 17 by the metal-organic chemical vapor deposition method, the deposition temperature is 50 to 300 ℃, the precursor (precursor) using 5 to 100 sccm (standard cubic centimeter per minute). Precursors include (hfac) CuTMVS and 0.1-20% TMVS, 0.1-10% Hhfac, 0.1-5% 1 / 2H 2 0 (hfac), 0.1-5% H 2 0 and the like. Mixtures containing additives such as (hfac) CuVTMOS and 0.1-20% VTMOS, 0.1-10% Hhfac, 0.1-5% 1 / 2H 2 0 (hfac), 0.1-5% H 2 0 A mixture of the above additives, and additives such as (hfac) CuPENTENE and 0.1-20% PENTENE, 0.1-10% Hhfac, 0.1-5% 1 / 2H 2 0 (hfac), 0.1-5% H 2 0 Any one of the mixtures containing the above additives is used.
한편, 전기도금법으로 구리층(17)을 증착할 경우, -20 내지 150℃의 저온에서 구리를 증착한다.On the other hand, when the copper layer 17 is deposited by electroplating, copper is deposited at a low temperature of -20 to 150 ° C.
도 1d를 참조하면, 구리층(17)을 형성한 후에 구리층 증착 챔버와 열처리 챔버의 진공도를 동일하게 유지하여 진공파괴 없이 수소 환원 분위기의 열처리 챔버에서 구리층(17)을 열처리한다. 이후, 패터닝 공정으로 구리 금속 배선을 형성한다. 상기 수소환원 분위기에서의 열처리는 200 내지 700℃의 온도에서 1분 내지 1시간 실시한다.Referring to FIG. 1D, after the copper layer 17 is formed, the copper layers 17 are heat treated in the heat treatment chamber in a hydrogen reduction atmosphere without vacuum destruction by maintaining the same vacuum degree of the copper layer deposition chamber and the heat treatment chamber. Thereafter, a copper metal wiring is formed by a patterning process. The heat treatment in the hydrogen reduction atmosphere is carried out for 1 minute to 1 hour at a temperature of 200 to 700 ℃.
상기에서 확산 방지막 및 구리 시드층을 물리기상증착법으로 형성하고, 구리층을 전기도금법으로 형성할 경우 진공파괴를 방지하기 위해 진공도를 E-8∼E-9Torr로 유지하고, 확산 방지막 및 구리 시드층을 화학기상증착법으로 형성하고, 구리층을 유기-금속 화학기상증착법으로 형성할 경우 진공파괴를 방지하기 위해 진공도를 E-3∼E-9Torr로 유지한다.In the above, the diffusion barrier and the copper seed layer are formed by physical vapor deposition, and when the copper layer is formed by the electroplating method, the vacuum degree is maintained at E-8 to E-9 Torr to prevent vacuum breakdown, the diffusion barrier and the copper seed layer. Is formed by chemical vapor deposition and the copper layer is maintained at E-3 to E-9 Torr to prevent vacuum breakage when the copper layer is formed by organic-metal chemical vapor deposition.
상기한 본 발명에 의하면, 구리 금속 배선을 얻기 위해 구리 전기도금법 또는 금속-유기 화학기상증착법을 이용할 때, 기존의 방법은 확산 방지막 및 시드층 형성 장비에서 확산 방지막 및 구리 시드층을 증착한 후에 진공파괴한 후 프리-클리닝하고, 전기도금법으로 구리를 증착 하는 방법을 사용하였다. 그러나, 본 발명의 기본적인 개념은, 전술한 바와 같이, 구리 금속 배선을 형성하기 위한 모든 공정을 전 공정의 챔버와 이후 공정의 챔버의 압력을 동일한 고진공 상태를 유지하여 진공파괴 없이 연속적으로 진행한다.According to the present invention described above, when using the copper electroplating method or metal-organic chemical vapor deposition method to obtain the copper metal wiring, the conventional method is vacuum after depositing the diffusion barrier film and the copper seed layer in the diffusion barrier film and seed layer forming equipment After destruction, pre-cleaning and copper plating were used by electroplating. However, according to the basic concept of the present invention, as described above, all the processes for forming the copper metal wirings are continuously performed without vacuum destruction while maintaining the same high vacuum state in the chambers of the pre-process and the post-process.
상술한 바와 같이, 본 발명은 구리 금속 배선을 형성하기 위한 모든 공정을 진공파괴 없이 연속적으로 진행하므로써, 기존에 필수적으로 진행하던 프리-클리닝 공정을 생략할 수 있을 뿐만 아니라, 구리 금속 배선의 신뢰성, 안정성 및 성능을 향상시킬 있고, 또한 진공파괴 없이 수소 환원 분위기에서 열처리를 행하여 구리층 형성 시에 발생되는 불순물이나 구리 산화막을 제거하여 구리 금속 배선의 전기적 특성을 향상시켜 보다 나은 소자 속도를 얻을 수 있는 장점을 가지고 있다.As described above, the present invention not only eliminates the pre-cleaning process that has been inevitably carried out by continuously performing all the processes for forming the copper metal wiring without vacuum breaking, but also the reliability of the copper metal wiring, It is possible to improve stability and performance, and to perform heat treatment in a hydrogen reducing atmosphere without vacuum breaking to remove impurities or copper oxides generated during copper layer formation to improve electrical characteristics of copper metal wirings, thereby obtaining better device speeds. It has advantages
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| KR100426209B1 (en) * | 2001-12-13 | 2004-04-06 | 김재정 | Fabricating Method of Copper Film for Semiconductor Interconnection |
| KR101051950B1 (en) * | 2003-12-15 | 2011-07-26 | 매그나칩 반도체 유한회사 | Manufacturing method of semiconductor device |
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| KR100586067B1 (en) * | 1999-06-23 | 2006-06-07 | 매그나칩 반도체 유한회사 | Method For Forming The CU Metal Line Using Electroplating |
| JP4300259B2 (en) * | 2001-01-22 | 2009-07-22 | キヤノンアネルバ株式会社 | Copper wiring film forming method |
| KR100465063B1 (en) * | 2002-04-01 | 2005-01-06 | 주식회사 하이닉스반도체 | Method for manufacturing metal interconnection layer of semiconductor device |
| KR100459723B1 (en) * | 2002-09-10 | 2004-12-03 | 삼성전자주식회사 | Method for fabricating semiconductor device having metal interconnections of different thickness |
| KR101229326B1 (en) * | 2011-03-31 | 2013-02-04 | 한국기계연구원 | Structure for measuring copper ion drift and measuring method for copper ion drift using the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100426209B1 (en) * | 2001-12-13 | 2004-04-06 | 김재정 | Fabricating Method of Copper Film for Semiconductor Interconnection |
| KR101051950B1 (en) * | 2003-12-15 | 2011-07-26 | 매그나칩 반도체 유한회사 | Manufacturing method of semiconductor device |
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