KR100282985B1 - Method for forming diffusion barrier metal of semiconductor devices - Google Patents
Method for forming diffusion barrier metal of semiconductor devices Download PDFInfo
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- KR100282985B1 KR100282985B1 KR1019990010296A KR19990010296A KR100282985B1 KR 100282985 B1 KR100282985 B1 KR 100282985B1 KR 1019990010296 A KR1019990010296 A KR 1019990010296A KR 19990010296 A KR19990010296 A KR 19990010296A KR 100282985 B1 KR100282985 B1 KR 100282985B1
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- Prior art keywords
- thin film
- metal thin
- titanium nitride
- vapor deposition
- titanium
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 93
- 239000002184 metal Substances 0.000 title claims abstract description 93
- 230000004888 barrier function Effects 0.000 title claims abstract description 19
- 238000009792 diffusion process Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title claims description 21
- 239000010409 thin film Substances 0.000 claims abstract description 65
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 45
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 30
- 239000010937 tungsten Substances 0.000 claims abstract description 30
- 239000010936 titanium Substances 0.000 claims abstract description 22
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 21
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 239000010408 film Substances 0.000 claims abstract description 17
- 238000009832 plasma treatment Methods 0.000 claims abstract description 14
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 11
- 239000000126 substance Substances 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 230000008021 deposition Effects 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 2
- 230000005855 radiation Effects 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 2
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 26
- 229910052710 silicon Inorganic materials 0.000 abstract description 26
- 239000010703 silicon Substances 0.000 abstract description 26
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 20
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- PXSHDOMYSLTUTJ-UHFFFAOYSA-N [Ti]N Chemical compound [Ti]N PXSHDOMYSLTUTJ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Abstract
콘택 홀 또는 비아 홀에서 균일하고 낮은 저항을 갖는 확산 장벽 금속을 형성하기 위하여, 트랜지스터 소자가 형성된 실리콘웨이퍼 상부에 절연막을 증착하고 패터닝하여 접촉 홀을 형성하고, 실리콘웨이퍼 전면에 물리 기상 증착으로 티타늄 금속 박막을 형성한다. 그리고, 화학 기상 증착으로 티타늄 금속 박막 상부에 티타늄 나이트라이드 금속 박막의 증착 및 H2/N2플라즈마 처리를 반복 실시한 후, 화학 기상 증착으로 텅스텐을 접촉 홀에 매입하고 화학 기계적 연마하여 평탄화하여 텅스텐 플러그를 형성하고, 그 상부 금속 패드를 형성하여 반도체 소자의 접촉 홀을 형성한다. 이와 같이 화학 기상 증착으로 티타늄 나이트라이드 금속 박막을 증착하므로 균일하고 낮은 접촉 저항을 갖는 확산 장벽 금속을 형성할 수 있을 뿐만 아니라 홀 입구에서의 돌출을 방지하고, H2/N2플라즈마 처리를 하여 티타늄 나이트라이드 금속 박막의 면저항을 감소시켜 홀의 접촉 저항을 감소시킴으로써 반도체 소자의 특성을 향상시킬 수 있다.In order to form a diffusion barrier metal having uniform and low resistance in the contact hole or the via hole, an insulating film is deposited and patterned on the silicon wafer on which the transistor element is formed to form a contact hole, and titanium metal is deposited on the silicon wafer by physical vapor deposition Form a thin film. After chemical vapor deposition, the titanium nitride metal thin film is deposited on the titanium metal thin film and H 2 / N 2 plasma treatment is repeatedly performed. Then, chemical vapor deposition is used to embed tungsten into contact holes, chemical mechanical polishing, and flatten the tungsten plug. The contact hole of the semiconductor element is formed by forming the upper metal pad. As a result of depositing the titanium nitride metal thin film by chemical vapor deposition, it is possible not only to form a diffusion barrier metal having a uniform and low contact resistance, but also to prevent protrusion at the hole entrance, and to treat the titanium by H 2 / N 2 plasma treatment. The characteristics of the semiconductor device may be improved by reducing the sheet resistance of the nitride metal thin film to reduce the contact resistance of the hole.
Description
본 발명은 반도체 소자의 제조 공정에 관한 것으로, 더욱 상세하게는 반도체 소자의 콘택(contact) 또는 비아(via) 등의 접촉 홀에서의 확산 장벽 금속(diffusion barrier metal)을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method of forming a diffusion barrier metal in contact holes such as contacts or vias of a semiconductor device.
일반적으로 반도체 소자를 제조하는 공정에서 실리콘웨이퍼에 트랜지스터 소자를 형성한 후, 칩 내부에서 절연막에 의해 전기적으로 절연된 각 소자를 전기적으로 접속하기 위하여 콘택을 형성하여 실리콘웨이퍼와 금속 배선을 연결하고 있으며, 특히 다선 배선에서 절연막에 의해 전기적으로 절연된 각 금속 배선간의 전기적 접속을 위하여 비아를 형성하고 있다.In general, in the process of manufacturing a semiconductor device, after forming a transistor device on a silicon wafer, a contact is formed to electrically connect each device electrically insulated by an insulating film inside the chip, thereby connecting the silicon wafer and the metal wiring. In particular, vias are formed for electrical connection between the metal wires electrically insulated by the insulating film in the multi-wire wiring.
이러한 콘택 또는 비아 등의 접촉 홀을 형성하기 위하여 현재 텅스텐 플러그가 일반적으로 이용되고 있다. 즉, 절연막에 의해 전기적으로 절연된 실리콘웨이퍼와 금속 배선 또는 금속 배선과 금속 배선을 전기적으로 접속하기 위하여 절연막에 콘택 홀 또는 비아 홀을 형성한 후, 텅스텐을 증착하여 콘택 홀 또는 비아 홀을 매입함으로써 전기적 접속이 이루어지도록 한다.Tungsten plugs are now commonly used to form contact holes such as contacts or vias. That is, by forming contact holes or via holes in the insulating film to electrically connect the silicon wafer and the metal wiring or the metal wiring and the metal wiring electrically insulated by the insulating film, and depositing tungsten by embedding the contact holes or via holes. Make electrical connections.
그리고, 텅스텐 플러그를 형성할 경우, 텅스텐 플러그 증착시 사용되는 WF6가스에 포함된 불소(F)에 의해 콘택홀 측벽의 절연막 및 하부벽의 금속 배선층 또는 실리콘웨이퍼의 손상을 방지 및 증착되는 텅스텐 박막과 절연막과의 접착력(adhesion)을 향상시키기 위한 글루층(glue layer)으로 이용하기 위하여 티타늄(Ti)/티타늄 나이트라이드(TiN)의 확산 장벽 금속을 텅스텐 증착전에 콘택 홀 또는 비아의 측벽 및 하부 벽에 형성하고 있다.In the case of forming a tungsten plug, a tungsten thin film is formed by preventing fluorine (F) contained in the WF 6 gas used for depositing the tungsten plug to prevent damage to the insulating layer on the sidewall of the contact hole and the metal wiring layer or silicon wafer on the lower wall. Sidewalls and bottom walls of the contact holes or vias prior to tungsten deposition of a diffusion barrier metal of titanium (Ti) / titanium nitride (TiN) for use as a glue layer to improve adhesion to the insulating film and the insulating film. To form.
그러면, 도 1a 내지 도 1d를 참조하여 종래 확산 장벽 금속 형성 방법에 따라 콘택 홀을 형성하는 공정을 개략적으로 설명한다.1A to 1D, a process of forming a contact hole according to a conventional diffusion barrier metal forming method will be schematically described.
먼저 도 1a에 도시한 바와 같이, 소자 분리 영역이 정의된 실리콘웨이퍼(1)의 각 정의된 소자 영역에 소스(S), 드레인(D) 및 게이트(G)가 형성된 트랜지스터 소자를 형성한 후, 실리콘웨이퍼(1) 전면에 TEOS(thetraethyleorthosilicate), BPSG(borophosphosilicateglass) 등의 절연막(2)을 증착한다. 그리고, 절연막(2)을 패터닝(patterning)하여 각 트랜지스터의 소스(S), 드레인(D) 및 게이트(G)의 상부가 드러나도록 콘택 홀을 형성한다. 이후, 실리콘웨이퍼(1) 전면에 물리 기상 증착(PVD ; physical vapor deposition)으로 티타늄 금속 박막(3)을 증착한다.First, as shown in FIG. 1A, a transistor device having a source S, a drain D, and a gate G is formed in each defined device region of the silicon wafer 1 in which the device isolation region is defined. An insulating film 2 such as tetraethyleorthosilicate (TEOS) or borophosphosilicate glass (BPSG) is deposited on the silicon wafer 1. Then, the insulating film 2 is patterned to form contact holes so that the upper portions of the source S, the drain D, and the gate G of each transistor are exposed. Thereafter, the titanium metal thin film 3 is deposited on the silicon wafer 1 by physical vapor deposition (PVD).
그 다음 도 1b에 도시한 바와 같이, 티타늄 금속 박막(3) 상부에 물리 기상 증착으로 티타늄 나이트라이드 금속 박막(4)을 증착한다. 이때, 티타늄/티타늄 나이트라이드 금속 박막(3)(4)은 콘택 홀에서의 확산 장벽 금속 역할을 한다.Then, as shown in FIG. 1B, the titanium nitride metal thin film 4 is deposited by physical vapor deposition on the titanium metal thin film 3. At this time, the titanium / titanium nitride metal thin film 3 and 4 serves as a diffusion barrier metal in the contact hole.
그 다음 도 1c에 도시한 바와 같이, 실리콘웨이퍼(1) 전면에 화학 기상 증착(CVD ; chemical vapor deposition)으로 텅스텐을 증착하여 콘택홀을 텅스텐으로 완전히 매입한 후, 화학 기계적 연마(CMP ; chemical mechanical polishing)하여 증착된 텅스텐을 평탄화하고, 절연막(2) 상부의 티타늄/티타늄 나이트라이드 금속 박막(3)(4)을 제거함으로써 콘택 홀의 텅스텐 플러그(5)를 형성한다.Then, as illustrated in FIG. 1C, tungsten is deposited by chemical vapor deposition (CVD) on the entire surface of the silicon wafer 1 to completely fill the contact holes with tungsten, and then chemical mechanical polishing (CMP; chemical mechanical). The deposited tungsten is planarized, and the tungsten plug 5 of the contact hole is formed by removing the titanium / titanium nitride metal thin films 3 and 4 on the insulating film 2.
그 다음 도 1d에 도시한 바와 같이, 물리 기상 증착에 의해 알루미늄을 증착하고, 패터닝하여 각 텅스텐 플러그(5) 상부에 알루미늄 금속 패드(6)를 형성함으로써 반도체 소자의 콘택을 완성한다.Then, as shown in FIG. 1D, aluminum is deposited by physical vapor deposition, and patterned to form aluminum metal pads 6 on each tungsten plug 5 to complete the contact of the semiconductor device.
이러한 종래의 확산 장벽 금속 형성 방법에서는 티타늄 나이트라이드를 물리 기상 증착하는 데, 물리 기상 증착은 금속 원자들이 여러 각도로 산란되어 증착되므로 금속 박막의 도포성(step coverage)이 나쁘다. 따라서 콘택 홀 또는 비아 홀 내부에 증착되는 금속의 두께는 홀 외부에 비하여 상대적으로 얇게 증착되며, 홀 입구에서 돌출(overhang)(도 1b의 7)이 형성된다.In the conventional diffusion barrier metal forming method, titanium nitride is physically vapor deposited. In the physical vapor deposition, metal atoms are scattered and deposited at various angles, so that the step coverage of the metal thin film is poor. Therefore, the thickness of the metal deposited in the contact hole or the via hole is relatively thinner than the outside of the hole, and an overhang (7 in FIG. 1B) is formed at the hole inlet.
이와 같이 홀 내부 모서리에서 증착된 금속 박막의 두께가 너무 얇으면, 텅스텐 금속 박막 형성시 텅스텐과 티타늄의 반응으로 휘발성(volatile)의 티타늄 테트라 프로라이드(TiF4)가 형성되어 금속 박막이 벗겨지거나(peeling), 텅스텐과 실리콘의 반응으로 트랜지스터의 소스/드레인 영역의 실리콘이 소모되어 접합(junction)을 파괴시켜 누설 전류(leakage current)가 발생되므로 트랜지스터 특성을 저하시키게 된다.If the thickness of the metal thin film deposited at the inner corner of the hole is too thin, a volatile titanium tetraproide (TiF 4 ) is formed by the reaction of tungsten and titanium when the tungsten metal thin film is formed, or the metal thin film is peeled off ( The peeling, reaction of tungsten and silicon consumes silicon in the source / drain region of the transistor, which breaks the junction, resulting in leakage current, thereby degrading transistor characteristics.
또한, 홀 입구에서의 돌출에 의해 후속 화학 기상 증착에 의한 텅스텐 금속 박막 형성시, 홀 입구가 먼저 막히게 되어 홀 내부가 완전히 텅스텐으로 매입되지 못하고 보이드(void)(도 1c의 8)가 형성된다. 이 보이드는 텅스텐 금속 박막에 대한 화학 기계적 연마시 화학 물질에 의한 침입(attack)으로 커지게 되고, 이에 따라 접촉 저항이 커지게 되어 트랜지스터 특성을 저하시키게 된다.In addition, when the tungsten metal thin film is formed by the subsequent chemical vapor deposition by the protrusion at the hole inlet, the hole inlet is blocked first, and a void (8 in FIG. 1C) is formed instead of being completely embedded in tungsten. This void becomes large due to the attack by chemicals during chemical mechanical polishing of the tungsten metal thin film, thereby increasing the contact resistance, thereby degrading transistor characteristics.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 접촉 홀에서의 균일하고 낮은 저항을 갖는 확산 장벽 금속을 형성하는 방법을 제공하는 데 있다.The present invention has been made to solve such a problem, and an object thereof is to provide a method of forming a diffusion barrier metal having a uniform and low resistance in a contact hole.
도 1a 내지 도 1d는 종래 확산 장벽 금속 형성 방법에 따라 콘택 홀을 형성하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이고,1A to 1D are cross-sectional views of silicon wafers schematically showing a process of forming contact holes according to a conventional diffusion barrier metal forming method,
도 2a 내지 도 2e는 본 발명에 따른 확산 장벽 금속 형성 방법에 따라 콘택 홀을 형성하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이다.2A to 2E are cross-sectional views of silicon wafers schematically showing a process of forming contact holes according to the diffusion barrier metal forming method according to the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 하부 도전막 상부의 절연막을 패터닝하여 콘택 홀 또는 비아 홀의 접촉 홀을 형성하고, 물리 기상 증착으로 티타늄 금속 박막을 증착한 후, 화학 기상 증착으로 티타늄 금속 박막 상부에 티타늄 나이트라이드 금속 박막을 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention is to form a contact hole of a contact hole or a via hole by patterning the insulating film on the lower conductive film, and depositing a titanium metal thin film by physical vapor deposition, and then by a chemical vapor deposition titanium metal Forming a titanium nitride metal thin film on the thin film.
또한, 본 발명은 상기 화학 기상 증착에 의한 티타늄 나이트라이드 금속 박막 증착 이후에 H2/N2플라즈마 처리를 하는 것을 특징으로 한다.In addition, the present invention is characterized in that the H 2 / N 2 plasma treatment after the deposition of the titanium nitride metal thin film by the chemical vapor deposition.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 확산 장벽 금속 형성 방법에 따라 콘택 홀을 형성하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이다.2A to 2E are cross-sectional views of silicon wafers schematically showing a process of forming contact holes according to the diffusion barrier metal forming method according to the present invention.
먼저 도 2a에 도시한 바와 같이, 소자 분리 영역이 정의된 실리콘웨이퍼(11)의 각 정의된 소자 영역에 소스(S), 드레인(D) 및 게이트(G)가 형성된 트랜지스터 소자를 형성한 후, 실리콘웨이퍼(11) 전면에 TEOS, BPSG 등의 절연막(12)을 증착한다. 그리고, 절연막(12)을 패터닝하여 각 트랜지스터의 소스(S), 드레인(D) 및 게이트(G)의 상부가 드러나도록 콘택 홀을 형성한다. 이후, 실리콘웨이퍼(11) 전면에 물리 기상 증착으로 티타늄 금속 박막(13)을 증착한다. 이때, 티타늄 금속 박막(13)을 증착하기전 수분 제거를 위한 디가스(degas)를 실시하며, 티타늄 금속 박막(13) 증착시 도포성을 향상시키기 위하여 콜리메이터(collimator)를 설치하는 것이 바람직하다.First, as shown in FIG. 2A, a transistor device having a source S, a drain D, and a gate G is formed in each defined device region of the silicon wafer 11 in which the device isolation region is defined. An insulating film 12 such as TEOS or BPSG is deposited on the silicon wafer 11. The insulating layer 12 is patterned to form contact holes so that the upper portions of the source S, the drain D, and the gate G of each transistor are exposed. Thereafter, the titanium metal thin film 13 is deposited by physical vapor deposition on the silicon wafer 11. At this time, before depositing the titanium metal thin film 13, it is preferable to perform degas for removing water, and to install a collimator in order to improve the coating property when the titanium metal thin film 13 is deposited.
그 다음 도 2b에 도시한 바와 같이, 실리콘웨이퍼 전면에 화학 기상 증착, 바람직하게는 TDMAT(tetrakis-dimethly amino titanium) 반응 가스를 이용한 화학 기상 증착으로 티타늄 금속 박막(13) 상부에 티타늄 나이트라이드 금속 박막(14)을 증착한다. 이때, 화학 기상 증착에 의한 티타늄 나이트라이드 금속 박막(14)의 증착시에는 접촉, 대류, 복사 등의 열전달을 통해 실리콘웨이퍼를 350℃ 내지 450℃ 정도로 가열하는 것이 바람직하다. 그리고, 티타늄 나이트라이드 금속 박막(14)을 도포성이 종래 물리 기상 증착에 비해 우수한 화학 기상 증착으로 증착하므로, 콘택 홀 내부에 증착되는 티타늄 나이트라이드 금속 박막은 콘택 홀 외부와 비슷한 두께로 증착되며, 홀 입구에서 돌출이 형성되지 않는다. 이후, 티타늄 나이트라이드 금속 박막(14)은 탄소(C)를 함유하고 있어 비저항이 높으므로, 실리콘웨이퍼 전면을 H2/N2플라즈마 처리를 하여 티타늄 나이트라이드 금속 박막(14)의 비저항을 낮춘다. 이때, 티타늄 나이트라이드 금속 박막(14)의 증착 두께는 150Å 정도로 하는 것이 바람직하다. 그러면, H2/N2플라즈마 처리시 증착된 티타늄 나이트라이드 금속 박막(14)이 50Å 정도 식각되고 잔류하는 티타늄 나이트라이드 금속 박막(14)의 두께는 100Å 정도가 되며, H2/N2플라즈마가 티타늄 나이트라이드 금속 박막 내부로 100Å 정도 침투되므로, 티타늄 나이트라이드 금속 박막(14) 내부의 탄소 함유량을 줄이므로 면저항이 감소된다.Next, as shown in FIG. 2B, a titanium nitride metal thin film on the titanium metal thin film 13 is formed by chemical vapor deposition on the silicon wafer, preferably by chemical vapor deposition using a tetrakis-dimethly amino titanium (TDMAT) reaction gas. (14) is deposited. At this time, when the titanium nitride metal thin film 14 is deposited by chemical vapor deposition, it is preferable to heat the silicon wafer to about 350 ° C. to about 450 ° C. through heat transfer such as contact, convection, and radiation. In addition, since the titanium nitride metal thin film 14 is deposited by chemical vapor deposition, which is superior in conventional physical vapor deposition, the titanium nitride metal thin film deposited inside the contact hole is deposited to a thickness similar to the outside of the contact hole, No protrusion is formed at the hole entrance. Afterwards, since the titanium nitride metal thin film 14 contains carbon (C) and has a high specific resistance, the entire surface of the silicon wafer is H 2 / N 2 plasma treated to lower the specific resistance of the titanium nitride metal thin film 14. At this time, the deposition thickness of the titanium nitride metal thin film 14 is preferably about 150 kPa. Then, the titanium nitride metal thin film 14 deposited during the H 2 / N 2 plasma treatment is etched about 50 μs, and the thickness of the remaining titanium nitride metal thin film 14 is about 100 μs, and the H 2 / N 2 plasma Since the titanium nitride metal thin film penetrates into the titanium nitride metal thin film by about 100 ms, the sheet resistance is reduced because the carbon content in the titanium nitride metal thin film 14 is reduced.
이와는 달리 티타늄 나이트라이드 금속 박막의 증착 및 H2/N2플라즈마 처리를 반복 실시할 수도 있다.Alternatively, the deposition of the titanium nitride metal thin film and the H 2 / N 2 plasma treatment may be repeated.
즉, 도 2c에 도시한 바와 같이, 실리콘웨이퍼 전면에 화학 기상 증착으로 티타늄 나이트라이드 금속 박막(14)을 증착한 후, H2/N2플라즈마 처리를 실시한다. 이때, 티타늄 나이트라이드 금속 박막(14)의 증착 두께를 100Å 정도로 하면, H2/N2플라즈마 처리시에 티타늄 나이트라이드 금속 박막(14)이 50Å 정도 식각되고 잔류하는 티타늄 나이트라이드 금속 박막(14)의 두께는 50Å 정도가 되며, H2/N2플라즈마가 티타늄 나이트라이드 금속 박막 내부로 100Å 정도 침투되므로, 티타늄 나이트라이드 금속 박막(14) 내부의 탄소 함유량을 줄이므로 면저항을 감소시킨다. 그리고, 재차 실리콘웨이퍼 전면에 화학 기상 증착으로 티타늄 나이트라이드 금속 박막(15)을 증착한 후, H2/N2플라즈마 처리를 실시한다. 이때, 티타늄 나이트라이드 금속 박막(15)의 증착 두께를 100Å 정도로 하면, H2/N2플라즈마 처리시에 티타늄 나이트라이드 금속 박막(15)이 50Å 정도 식각되고 잔류하는 티타늄 나이트라이드 금속 박막(15)의 두께는 50Å 정도가 되며, H2/N2플라즈마가 티타늄 나이트라이드 금속 박막 내부로 100Å 정도 침투되므로, 티타늄 나이트라이드 금속 박막(15) 내부의 탄소 함유량을 줄이므로 면저항을 감소시킨다.That is, as shown in Fig. 2c, after the titanium nitride metal thin film 14 is deposited by chemical vapor deposition on the entire surface of the silicon wafer, H 2 / N 2 plasma treatment is performed. At this time, when the deposition thickness of the titanium nitride metal thin film 14 is about 100 GPa, the titanium nitride metal thin film 14 is etched and remains about 50 GPa during the H 2 / N 2 plasma treatment. The thickness of is about 50 kPa, H 2 / N 2 plasma penetrates about 100 kPa into the titanium nitride metal thin film, reducing the carbon content in the titanium nitride metal thin film 14, thereby reducing the sheet resistance. Then, after the titanium nitride metal thin film 15 is deposited by chemical vapor deposition on the entire silicon wafer, H 2 / N 2 plasma treatment is performed. At this time, when the deposition thickness of the titanium nitride metal thin film 15 is about 100 GPa, the titanium nitride metal thin film 15 is etched and remains about 50 GPa during the H 2 / N 2 plasma treatment. The thickness of is about 50 kPa, H 2 / N 2 plasma penetrates about 100 kPa into the titanium nitride metal thin film, thereby reducing the carbon content in the titanium nitride metal thin film 15, thereby reducing the sheet resistance.
즉, 티타늄 나이트라이드 금속 박막의 면저항을 감소시키기 위하여, 적정 두께의 티타늄 나이트라이드 금속 박막 형성과 H2/N2플라즈마 처리 공정을 2회 이상 반복 실시할 수도 있다.That is, in order to reduce the sheet resistance of the titanium nitride metal thin film, a titanium nitride metal thin film having an appropriate thickness and H 2 / N 2 plasma treatment may be repeatedly performed two or more times.
그 다음 도 2d에 도시한 바와 같이, 실리콘웨이퍼(11) 전면에 화학 기상 증착으로 텅스텐을 증착하여 콘택 홀을 텅스텐으로 완전히 매입한 후, 화학 기계적 연마하여 증착된 텅스텐을 평탄화하고, 절연막(12) 상부의 티타늄/티타늄 나이트라이드 금속 박막(13)(14, 15)을 제거함으로써 콘택 홀의 텅스텐 플러그(16)를 형성한다. 이때, 콘택 홀 내부 모서리에서도 티타늄 나이트라이드 금속 박막(14, 15)이 균일하게 증착되어 있으므로 텅스텐의 증착시, 종래와 같이 텅스텐과 티타늄 금속 박막(13)의 반응으로 휘발성의 티타늄 테트라 프로라이드가 형성되어 박막(13)이 벗겨지거나, 텅스텐과 실리콘의 반응으로 트랜지스터의 소스(S), 드레인(D) 영역의 실리콘이 소모되어 접합을 파괴시켜 누설 전류가 발생되는 현상을 방지할 수 있어 트랜지스터 특성 저하를 방지할 수 있다. 또한, 콘택 홀 입구에서의 돌출이 형성되지 않으므로 텅스텐 증착시 콘택 홀 내부가 완전히 매입지게 된다. 따라서, 후속 화학 기계적 연마 공정에서 화학 물질에 의한 침입을 받지 않으므로 접촉 저항이 낮아져 트랜지스터 특성을 향상시키게 된다.Next, as shown in FIG. 2D, tungsten is deposited by chemical vapor deposition on the entire surface of the silicon wafer 11 to completely fill the contact holes with tungsten, and then chemical mechanical polishing is used to planarize the deposited tungsten, and the insulating film 12 The tungsten plug 16 of the contact hole is formed by removing the upper titanium / titanium nitride metal thin film 13 (14, 15). At this time, since the titanium nitride metal thin films 14 and 15 are uniformly deposited on the inner corners of the contact holes, volatile titanium tetraproide is formed by the reaction of tungsten and the titanium metal thin film 13 as in the prior art when tungsten is deposited. The thin film 13 is peeled off or the reaction of tungsten and silicon consumes silicon in the source (S) and drain (D) regions of the transistor, which breaks the junction and prevents leakage current. Can be prevented. In addition, since the protrusion at the contact hole inlet is not formed, the inside of the contact hole is completely filled during tungsten deposition. As a result, the contact resistance is lowered because the chemicals are not invaded by a subsequent chemical mechanical polishing process, thereby improving transistor characteristics.
그 다음 도 2e에 도시한 바와 같이, 물리 기상 증착에 의해 알루미늄을 증착하고, 패터닝하여 각 텅스텐 플러그(16) 상부에 알루미늄 금속 패드(17)를 형성함으로써 반도체 소자의 콘택을 완성한다.Then, as shown in FIG. 2E, aluminum is deposited and patterned by physical vapor deposition to form an aluminum metal pad 17 on each tungsten plug 16 to complete the contact of the semiconductor device.
상기의 실시예에서는 콘택 홀에서의 확산 장벽 금속 형성 방법을 설명하였지만, 비아 홀에서도 같은 방법에 의해 균일하고 낮은 접촉 저항을 갖는 확산 장벽 금속을 형성할 수 있다.In the above embodiment, the method of forming the diffusion barrier metal in the contact hole has been described, but the diffusion barrier metal having the uniform and low contact resistance can be formed by the same method in the via hole.
이와 같이 본 발명은 화학 기상 증착으로 티타늄 나이트라이드 금속 박막을 증착하므로 균일하고 낮은 접촉 저항을 갖는 확산 장벽 금속을 형성할 수 있을 뿐만 아니라 홀 입구에서의 돌출을 방지할 수 있으며, 티타늄 나이트라이드 금속 박막 증착하고 H2/N2플라즈마 처리를 하여 티타늄 나이트라이드 금속 박막의 면저항을 감소시켜 접촉 홀에서의 접촉 저항을 감소시킴으로써 반도체 소자의 특성을 향상시킬 수 있다.As described above, the present invention deposits a titanium nitride metal thin film by chemical vapor deposition, which not only forms a diffusion barrier metal having a uniform and low contact resistance, but also prevents protrusion at a hole inlet. Deposition and H 2 / N 2 plasma treatment can reduce the sheet resistance of the titanium nitride metal thin film to reduce the contact resistance in the contact hole, thereby improving the characteristics of the semiconductor device.
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| KR1019990010296A KR100282985B1 (en) | 1999-03-25 | 1999-03-25 | Method for forming diffusion barrier metal of semiconductor devices |
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| KR100755053B1 (en) * | 2001-12-14 | 2007-09-06 | 주식회사 하이닉스반도체 | Method for forming bit line of semiconductor device |
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| KR100445552B1 (en) * | 2001-06-28 | 2004-08-21 | 동부전자 주식회사 | Contact plug for a semiconductor device and method for fabricating the same |
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| KR100755053B1 (en) * | 2001-12-14 | 2007-09-06 | 주식회사 하이닉스반도체 | Method for forming bit line of semiconductor device |
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