KR0179168B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR0179168B1 KR0179168B1 KR1019950006202A KR19950006202A KR0179168B1 KR 0179168 B1 KR0179168 B1 KR 0179168B1 KR 1019950006202 A KR1019950006202 A KR 1019950006202A KR 19950006202 A KR19950006202 A KR 19950006202A KR 0179168 B1 KR0179168 B1 KR 0179168B1
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- South Korea
- Prior art keywords
- forming
- ion implantation
- semiconductor device
- gate electrode
- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 230000000694 effects Effects 0.000 abstract description 7
- 125000001475 halogen functional group Chemical group 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 숏채널 효과의 발생을 줄이고 할로 구조의 단점을 향상시키는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for reducing the occurrence of a short channel effect and improving a disadvantage of a halo structure.
본 발명은 상기 목적을 달성하기 위해 제1도전형 반도체 기판상에 게이트 절연막을 사이에 두고 게이트 전극을 형성하는 공정과, 상기 게이트 전극 양측의 상기 기판내에 저농도 LDD영역을 형성하는 공정과, 상기 게이트 전극 양측의 기판이 소정부분 노출되도록 소켓 이온주입용 마스크를 형성하는 공정과, 경사이온주입을 통해 상기 게이트 전극 양쪽의 채널쪽 접합부위에 제1도전형의 포켓팅 영역을 형성하는 공정과, 상기 게이트 전극 양측면에 측벽을 형성한 후 고농도의 소오스/드레인 불순물 이온주입을 실시하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The present invention provides a process for forming a gate electrode on a first conductive semiconductor substrate with a gate insulating film interposed therebetween; forming a low concentration LDD region in the substrate on both sides of the gate electrode; Forming a socket ion implantation mask to expose a predetermined portion of the substrate on both sides of the electrode, forming a first conductive type pocketing region on the channel side junctions of both gate electrodes through gradient ion implantation, and the gate And forming a sidewall on both sides of the electrode and then performing a high concentration source / drain impurity ion implantation.
Description
제1도는 종래의 반도체 소자 공정 단면도.1 is a cross-sectional view of a conventional semiconductor device process.
제2도는 본 발명의 반도체 소자 공정 단면도.2 is a cross-sectional view of a semiconductor device process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : P형 기판 2 : 게이트 산화막1: P-type substrate 2: Gate oxide film
3 : 게이트 전극 4 : 저농도 n형 이온주입3: gate electrode 4: low concentration n-type ion implantation
4a : LDD영역 5 : 문턱전압 조절용 마스크4a: LDD area 5: mask for adjusting threshold voltage
6 : p형 틸트 이온주입 7 : p층 포켓팅6: p-type tilt ion implantation 7: p-layer pocketing
8 : 게이트 측벽 9 : 고농도 n형 이온주입8: gate sidewall 9: high concentration n-type ion implantation
9a : 소오스 및 드레인 영역9a: source and drain regions
본 발명은 반도체 소자 제조방법에 관한 것으로 특히, 숏채널 효과(short channel effect)와, 소오스 및 드레인에서 발생되는 기생용량을 줄이기에 적당한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for reducing short channel effects and parasitic capacitances generated from sources and drains.
일반적으로 소자의 집적도가 증가하면 채널 길이(channel length)가 감소하고, 소오스 및 드레인 접합깊이(junction depth)가 감소한다.In general, as the integration of devices increases, channel lengths decrease and source and drain junction depths decrease.
그래서 펀치 스로우(punch through)등 숏채널 현상이 발생하여 소자의 특성과문턱전압(threshold voltage) 등의 특성 불안정을 야기시킨다.As a result, a short channel phenomenon such as punch through occurs, which causes device characteristics and characteristic instability such as a threshold voltage.
따라서, 숏채널 현상을 방지하기 위해서 할로 구조를 갖는 MOSFET가 개발되었다.Therefore, a MOSFET having a halo structure has been developed to prevent the short channel phenomenon.
이와 같은 종래의 반도체 소자 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional semiconductor device manufacturing method is as follows.
제1도는 종래 반도체 소자의 공정 단면도이다.1 is a cross-sectional view of a conventional semiconductor device.
제1도 (a)와 같이, p형 기판(1)위에 게이트 산화막(2)을 증착시키고, 연이어 게이트 산화막(2)위에 게이트 전극(3)을 형성한다.As shown in FIG. 1A, a gate oxide film 2 is deposited on the p-type substrate 1, and subsequently, a gate electrode 3 is formed on the gate oxide film 2.
상기 게이트 전극(3)을 마스크로 이용하여 핫 캐리어(hot carrier)효과를 방지하기 위해 기판(1)에 저농도(n-)n형 이온주입(4)을 실시하여 LDD(Lightly Doped Drain)영역(4a)을 형성한다.In order to prevent a hot carrier effect by using the gate electrode 3 as a mask, a low concentration (n − ) n type ion implantation 4 is applied to the substrate 1 so that a lightly doped drain (LDD) region ( 4a).
제1도 (b)와 같이, 소오스와 드레인간의 내압 저하를 개선하고, 문턱전압 감소를 방지하기 위해서 p형 이온을 틸트(tilt)주입(6)하여 LDD영역을 감싸도록 할로 구조(holo structure)를 갖는 p층 포켓팅(pocketing)(7)을 형성한다.As shown in FIG. 1B, in order to improve the breakdown voltage between the source and the drain, and to prevent the threshold voltage from being reduced, a plow type ions are injected into the p-type ion to surround the LDD region. To form a p-layer pocketing (7).
제1도 (c)와 같이, 전면에 저압산화막을 증착하고, 비등방성 건식식각을 실시하여 게이트 전극(3) 측면에 측벽(8)을 형성한 다음, 고농도 n형 이온주입(9)으로 소오스 및 드레인(9a)을 형성한다.As shown in FIG. 1 (c), a low pressure oxide film is deposited on the entire surface, and anisotropic dry etching is performed to form sidewalls 8 on the side of the gate electrode 3, and then sourced with a high concentration n-type ion implantation 9. And a drain 9a.
이와 같이 제조하여 종래의 반도체 소자는 숏채널 효과에 기인하는 문턱전압 감소와, 소오스 드레인간의 내압저하를 개선시켰으나, 소오스, 드레인간의 기생용량이 증가되므로 스위칭 속도가 저하되는 소자특성이 나빠지는 문제점이 있었다.In this way, the conventional semiconductor device has improved the threshold voltage due to the short channel effect and the decrease in the breakdown voltage between the source and drain, but the parasitic capacitance between the source and the drain is increased, resulting in a deterioration of the device characteristic of the switching speed. there was.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로, p형 포켓팅 형성시 문턱전압 조절용 마스크를 이용하여 이온주입을 행함으로써, 소오스 및 드레인영역의 채널쪽 접합부에만 p층 포켓팅 영역을 형성하여 소오스/드레인간의 내압저하 및 문턱전압 감소를 방지함은 물론 소오스 및 드레인간의 기생용량을 감소시켜 소자특성을 향상시키는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by forming an ion implantation using a mask for adjusting the threshold voltage when forming p-type pocketing, a p-layer pocketing region is formed only at the channel side junctions of the source and drain regions. Therefore, the purpose of the present invention is to improve the device characteristics by reducing the breakdown voltage between the source and drain and reducing the threshold voltage, as well as reducing the parasitic capacitance between the source and the drain.
상기의 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은 제1도전형 반도체 기판상에 게이트 절연막을 사이에 두고 게이트 전극을 형성하는 공정과, 상기 게이트 전극 양측의 상기 기판내에 저농도 LDD영역을 형성하는 공정과, 상기 게이트 전극 양측의 기판이 소정부분 노출되도록 소켓 이온주입용 마스크를 형성하는 공정과, 경사이온주입을 통해 상기 게이트 전극 양쪽의 채널쪽 접합부위에 제1도전형의 포켓팅 영역을 형성하는 공정과, 상기 게이트 전극 양측면에 측벽을 형성한 후 고농도의 소오스/드레인 불순물 이온주입을 실시하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming a gate electrode on the first conductive semiconductor substrate with a gate insulating film interposed therebetween, and forming a low concentration LDD region in the substrate on both sides of the gate electrode Forming a socket ion implantation mask so as to expose a predetermined portion of the substrates on both sides of the gate electrode; and forming a first conductive pocketing region on the channel side junctions of both gate electrodes through inclined ion implantation. And a step of forming sidewalls on both sides of the gate electrode and then performing a high concentration source / drain impurity ion implantation.
상기와 같은 본 발명의 반도체 소자 제조방법을 첨부된 도면을 참조하여 보다 상세히 설명하면 다음과 같다.The semiconductor device manufacturing method of the present invention as described above will be described in more detail with reference to the accompanying drawings.
제2도는 본 발명의 반도체 소자의 공정 단면도이다.2 is a cross-sectional view of the semiconductor device of the present invention.
제2도 (a)와 같이, p형 기판(1)의 전면에 게이트 산화막(2)을 형성하고, 연이어 게이트 산화막(2)위에 게이트 전극(3)을 형성하고, 게이트 전극(3)을 마스크로 이용하여 핫캐리어 효과의 발생을 방지하기 위해 저농도 n형 이온주입(4)으로 소오스 및 드레인의 LDD영역(4a)을 형성한다.As shown in FIG. 2A, a gate oxide film 2 is formed on the entire surface of the p-type substrate 1, a gate electrode 3 is subsequently formed on the gate oxide film 2, and the gate electrode 3 is masked. In order to prevent the occurrence of the hot carrier effect, the LDD region 4a of the source and drain is formed by the low concentration n-type ion implantation 4.
제2도 (b)와 같이, p형 틸트(tilt)이온주입을 실시하기 전에 블록킹(blocking)용 문턱전압 조절용 마스크를 형성하여 p형 틸트 이온주입(6)을 실시하면, 채널쪽 접합부에만 p층 포켓팅(7)영역이 형성된다.As shown in FIG. 2 (b), when the blocking threshold voltage adjustment mask is formed and the p-type tilt ion implantation 6 is performed before the p-type tilt ion implantation is performed, only p is connected to the channel side junction. The layer pocketing 7 region is formed.
제2도 (c)와 같이, 전면에 산화막을 증착하고, 비등방성 건식식각을 실시하여 게이트 전극(3) 측면에 산화막 측벽(8)을 형성한 후, 고농도 n형 (n+) 불순물 이온주입(9)으로 소오스 및 드레인 영역(9a)을 형성한다.As shown in FIG. 2 (c), an oxide film is deposited on the entire surface, and anisotropic dry etching is performed to form an oxide film sidewall 8 on the side of the gate electrode 3, and then a high concentration of n-type (n + ) impurity ions are implanted. (9) forms source and drain regions 9a.
이와 같은 본 발명은 반도체 소자 제조시, 발생하는 기생접합 용량을 줄이므로써 회로의 성능을 향상시키고, 숏채널 효과에 의한 문턱전압 저하 및 소오스/드레인간의 내압저하를 방지하는 효과가 있다.The present invention improves the performance of the circuit by reducing the parasitic junction capacitance generated during semiconductor device manufacturing, and has the effect of preventing the threshold voltage drop due to the short channel effect and the breakdown voltage between the source and drain.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006202A KR0179168B1 (en) | 1995-03-23 | 1995-03-23 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006202A KR0179168B1 (en) | 1995-03-23 | 1995-03-23 | Method for fabricating semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR960035917A KR960035917A (en) | 1996-10-28 |
| KR0179168B1 true KR0179168B1 (en) | 1999-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950006202A KR0179168B1 (en) | 1995-03-23 | 1995-03-23 | Method for fabricating semiconductor device |
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| Country | Link |
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| KR (1) | KR0179168B1 (en) |
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1995
- 1995-03-23 KR KR1019950006202A patent/KR0179168B1/en not_active IP Right Cessation
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| KR960035917A (en) | 1996-10-28 |
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