JPWO2019216085A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Abstract
Description
実施の形態にかかる半導体装置の製造方法について、FWD領域にヘリウム(He)照射によりヘリウムの欠陥を導入した耐圧1200VクラスのRC−IGBTを例に説明する。耐圧とは、素子が誤動作や破壊を起こさない限界の電圧である。図1は、実施の形態にかかる半導体装置の製造方法の一部の工程の概要を示すフローチャートである。図2〜図4は、実施の形態にかかる半導体装置の製造方法の一部の工程における半導体装置の製造途中の状態を模式的に示す断面図である。
2、102 p型ベース領域
3、103 n+型エミッタ領域
4、104 p+型コンタクト領域
5、105 n型蓄積層
6、106 トレンチ
7、107 ゲート絶縁膜
8、108 ゲート電極
9、109 層間絶縁膜
10、110 半導体ウエハ
10a 半導体ウエハのおもて面
10b 半導体ウエハの裏面
11、111 おもて面電極
12、112 n型フィールドストップ層
13、113 p+型コレクタ領域
14、114 n+型カソード領域
15、115 欠陥
16 保護膜
17 保護膜
18、118 アライメントマーク
21、121 IGBT領域
22、122 FWD領域
23 デバイス領域
24 ウエハ端部
25 デバイス領域外周端
26 剥離面
31、131 メタルマスク
32、132 He照射
33 開口部
34 アライメント孔
35 プレート
36 保持片
37 保持部
140 異物
Claims (8)
- 第1導電型の半導体基板の一方の主面側に半導体素子のおもて面素子構造を形成する第1工程と、
前記半導体基板の他方の主面側に第1保護膜を形成する第2工程と、
前記第1保護膜を形成した主面側から前記半導体基板にイオンを注入する第3工程と、
前記第1保護膜を除去する第4工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第1工程より後、前記第3工程より前に、
前記半導体基板の一方の主面側に第2保護膜を形成する第5工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1保護膜と前記第2保護膜は、同様の材料から形成されることを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記第2工程では、前記半導体基板の端部には前記第1保護膜を形成しないことを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記第2工程では、前記第1保護膜にアライメントマークを形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第5工程では、前記第2保護膜にアライメントマークを形成することを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記第1工程では、前記半導体基板の前記一方の主面側にアライメントマークを形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1工程と前記第2工程との間に前記半導体基板の他方の主面を研削する工程をさらに含むことを特徴とする請求項1〜7のいずれか一つに記載の半導体装置の製造方法。
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