JPWO2013147276A1 - 縦型高耐圧半導体装置および縦型高耐圧半導体装置の製造方法 - Google Patents
縦型高耐圧半導体装置および縦型高耐圧半導体装置の製造方法 Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 67
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Abstract
Description
以下、本発明の実施例1について、図5を参照して説明する。図5は、実施例1のSiC−MOSFETの各製造工程における断面図であり、図5(a)はP+層を結合していない部分、図5(b)はP+層(IGBTの場合は、P+基板)を結合している部分の断面図を示している。本実施例1においては、縦型プレーナーゲートMOSFETとして、半導体材料として炭化ケイ素(SiC)を用い、素子耐圧1200VのMOSFETを例に挙げて説明する。
つぎに、この発明にかかる実施例2について説明する。実施例2においては、実施例1と同様の製造工程により作製した、1200V・25AのMOSFETを例にして説明する。実施例2においては、N型SiC半導体基板1の結晶学的面指数が(0001)に対して4度程度傾いた面の上に、窒素を1.8×1016cm-3程度含むN型SiC層2を10μm程度エピタキシャル成長させた。実施例2において、N型SiC層2以外を形成する工程やセル構造については、上述した実施例1とすべて同一であるため、説明を省略する。
つぎに、この発明にかかる実施例3について説明する。実施例3においては、実施例1と同様の製造工程により作製した、1200V・25AのMOSFETを例にして説明する。実施例3においては、N型SiC半導体基板1の結晶学的面指数が(000−1)に対して4度程度傾いた面の上に、窒素を1.8×1016cm-3程度含むN型SiC層2を、10μm程度エピタキシャル成長させた。
つぎに、この発明にかかる実施例4について説明する。実施例4においては、まず、半導体基板1としてN型SiC半導体基板を用意する。実施例4では、不純物として窒素を2×1019cm-3程度含む低抵抗N型SiC半導体基板1を半導体基板とする。実施例4においては、N型SiC半導体基板1の結晶学的面指数が(000−1)に対して4度程度傾いた面の上に、たとえば、窒素を1.8×1016cm-3程度含むN型SiC層2を、10μm程度エピタキシャル成長させる。
つぎに、この発明にかかる実施例5について説明する。実施例5においては、実施例4と同様の製造工程により作製した、1200V・25AのMOSFETを例にして説明する。実施例5においては、N型SiC半導体基板1の結晶学的面指数が(0001)に対して4度程度傾いた面の上に、窒素を1.8×1016cm-3程度含むN型SiC層2を10μm程度エピタキシャル成長させた。その他の工程は、実施例4とすべて同一とする。
2 第1の半導体層
3 P+層
4 Pベース層
6 N打ち返し層
7 N+ソース層
8 P+コンタクト層
9 ゲート絶縁膜
10 ゲート電極
11 ソース電極
12 ドレイン電極
13 連結部
Claims (6)
- 第1導電型の半導体基板(1)と、
前記半導体基板(1)上に形成された第1導電型で前記半導体基板(1)よりも不純物濃度が低い第1の半導体層(2)と、
前記第1の半導体層(2)の表面に選択的に形成された第2導電型で第1の半導体層(2)よりも不純物濃度が高い第2の半導体層(3)と、
前記第1の半導体層(2)および前記第2の半導体層(3)の上に設けられた第2導電型のベース層(4)と、
前記ベース層(4)の表面層に選択的に形成された第1導電型ソース領域(7)と、
表面から前記ベース層(4)を貫通して前記第1の半導体層(2)に達するように形成された第1導電型のN打ち返し層(6)と、
前記ソース領域(7)と前記N打ち返し層(6)とに挟まれた前記ベース層(4)の表面露出部上の少なくとも一部にゲート絶縁膜(9)を介して設けられたゲート電極層(10)と、
前記ソース領域(7)と前記ベース層(4)との表面に共通に接触するソース電極(11)と、
前記半導体基板(1)の裏面に設けられたドレイン電極(12)と、
を有する縦型高耐圧半導体装置であって、
前記第2の半導体層(3)の一部は、前記N打ち返し層(6)の下の領域で互いに結合されていることを特徴とする縦型高耐圧半導体装置。 - 前記第2の半導体層(3)の一部が前記N打ち返し層(6)の下の領域で結合されている部分は、前記ベース層(4)と前記N打ち返し層(6)で形成されるPN接合から離隔していることを特徴とする請求項1に記載の縦型高耐圧半導体装置。
- 前記半導体基板(1)の半導体材料が炭化ケイ素であることを特徴とする請求項1または2に記載の縦型高耐圧半導体装置。
- 前記半導体基板(1)の結晶学的面指数が(000−1)に対して平行な面もしくは10度以内に傾いた面であることを特徴とする請求項3に記載の縦型高耐圧半導体装置。
- 前記半導体基板(1)の結晶学的面指数が(0001)に対して平行な面もしくは10度以内に傾いた面であることを特徴とする請求項4に記載の縦型高耐圧半導体装置。
- 第1導電型の半導体基板(1)上に第1導電型で前記半導体基板(1)よりも不純物濃度が低い第1の半導体層(2)を形成する工程と、
前記第1の半導体層(2)の表面に、第2導電型で第1の半導体層(2)よりも不純物濃度が高い第2の半導体層(3)をイオン注入法により選択的に形成する工程と、
前記第1の半導体層(2)および前記第2の半導体層(3)の上に、エピタキシャル成長法により第2導電型のベース層(4)を形成する工程と、
前記ベース層(4)の表面層に選択的に形成された第1導電型ソース領域(7)と、表面から前記ベース層(4)を貫通して前記第1の半導体層(2)に達する第1導電型のN打ち返し層(6)と、をイオン注入法により形成する工程と、
を含み、
前記第2の半導体層(3)を形成する工程は、前記第2の半導体層(3)の一部が、前記N打ち返し層(6)の下の領域で互いに結合されるように形成することを特徴とする縦型高耐圧半導体装置の製造方法。
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US9881997B2 (en) * | 2015-04-02 | 2018-01-30 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
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