JPS6484491A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make an access time faster and to obtain sufficient margins of an address setup and writing recovery by performing the equalizing and precharging of a bit wire at high speed after the completion of writing, and quickening the rise of a word wire. CONSTITUTION:Since an H level supplied from a writing circuit 6 to data lines D and the inverse of D pass through Q14 and Q15, it is lower by the threshold voltage of a transistor than a supply voltage Vdd, and is equal to the precharging voltage of the bit wire and the data wire. Consequently, by simultaneously supplying the H level to a pair of the data wires D and the inverse of D, it is possible to make the bit wire and the data wire into a precharged condition. For the writing circuit 6, when the inverse of WE is at the L level, NAND circuits 8 and 9 output offset data. Thus, by constituting the titled device as the above, the equalizing and precharging of the bit wire after the completion of the writing can be performed at high speed, the access time is made faster, and the margins of the address setup and the writing recovery can be sufficiently obtained.