JPS6481348A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6481348A
JPS6481348A JP62239180A JP23918087A JPS6481348A JP S6481348 A JPS6481348 A JP S6481348A JP 62239180 A JP62239180 A JP 62239180A JP 23918087 A JP23918087 A JP 23918087A JP S6481348 A JPS6481348 A JP S6481348A
Authority
JP
Japan
Prior art keywords
terminals
adhered
ics
disposed
tapes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62239180A
Other languages
Japanese (ja)
Other versions
JP2631665B2 (en
Inventor
Ryutaro Arakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxell Holdings Ltd
Original Assignee
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Maxell Ltd filed Critical Hitachi Maxell Ltd
Priority to JP62239180A priority Critical patent/JP2631665B2/en
Publication of JPS6481348A publication Critical patent/JPS6481348A/en
Application granted granted Critical
Publication of JP2631665B2 publication Critical patent/JP2631665B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To reduce malfunctions at the time of reflow adhering, to reduce punch forming metal molds and to improve production efficiency by connecting corresponding lead terminals of a plurality of IC chips before the chips are isolated from a film tape at the time of mounting them in multi-stage. CONSTITUTION:Film tapes 6, 6 for placing memory ICs 15 are disposed at a predetermined interval in upper and lower stages, corresponding lead terminals 5 are adhered in a state that the ICs 15 are disposed on the tapes 6, 6, the two ICs 15 are simultaneously fed, and mounted on a printed substrate. Since the lead terminals are punch-formed to the 2 ICs 15 with the corresponding terminals 5 adhered, the thickness of the terminals 5 become thick so that its bent scarcely occur advantageously. The type of metal mold may be only one, and since the terminals 5 are adhered in advance even when substrate terminals 11 are adhered to the terminals 5 by reflowing, a malfunction scarcely occur.
JP62239180A 1987-09-24 1987-09-24 Manufacturing method of stacked semiconductor device Expired - Fee Related JP2631665B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62239180A JP2631665B2 (en) 1987-09-24 1987-09-24 Manufacturing method of stacked semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62239180A JP2631665B2 (en) 1987-09-24 1987-09-24 Manufacturing method of stacked semiconductor device

Publications (2)

Publication Number Publication Date
JPS6481348A true JPS6481348A (en) 1989-03-27
JP2631665B2 JP2631665B2 (en) 1997-07-16

Family

ID=17040913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62239180A Expired - Fee Related JP2631665B2 (en) 1987-09-24 1987-09-24 Manufacturing method of stacked semiconductor device

Country Status (1)

Country Link
JP (1) JP2631665B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02174255A (en) * 1988-12-27 1990-07-05 Mitsubishi Electric Corp Semiconductor integrated circuit
JPH02290048A (en) * 1989-02-15 1990-11-29 Matsushita Electric Ind Co Ltd Laminated semiconductor mounted body
JPH0323998A (en) * 1989-06-20 1991-01-31 Matsushita Electric Ind Co Ltd Ic memory card
JPH0323995A (en) * 1989-06-20 1991-01-31 Matsushita Electric Ind Co Ltd Ic memory card
US5394608A (en) * 1992-04-08 1995-03-07 Hitachi Maxwell, Ltd. Laminated semiconductor device and fabricating method thereof
US5656547A (en) * 1994-05-11 1997-08-12 Chipscale, Inc. Method for making a leadless surface mounted device with wrap-around flange interface contacts
WO1998025305A1 (en) * 1996-12-04 1998-06-11 Hitachi, Ltd. Method for manufacturing semiconductor device
WO1998025304A1 (en) * 1996-12-04 1998-06-11 Hitachi, Ltd. Semiconductor device
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662351A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor device for memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662351A (en) * 1979-10-26 1981-05-28 Hitachi Ltd Semiconductor device for memory

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02174255A (en) * 1988-12-27 1990-07-05 Mitsubishi Electric Corp Semiconductor integrated circuit
JPH02290048A (en) * 1989-02-15 1990-11-29 Matsushita Electric Ind Co Ltd Laminated semiconductor mounted body
JPH0323998A (en) * 1989-06-20 1991-01-31 Matsushita Electric Ind Co Ltd Ic memory card
JPH0323995A (en) * 1989-06-20 1991-01-31 Matsushita Electric Ind Co Ltd Ic memory card
US5394608A (en) * 1992-04-08 1995-03-07 Hitachi Maxwell, Ltd. Laminated semiconductor device and fabricating method thereof
US5656547A (en) * 1994-05-11 1997-08-12 Chipscale, Inc. Method for making a leadless surface mounted device with wrap-around flange interface contacts
WO1998025305A1 (en) * 1996-12-04 1998-06-11 Hitachi, Ltd. Method for manufacturing semiconductor device
WO1998025304A1 (en) * 1996-12-04 1998-06-11 Hitachi, Ltd. Semiconductor device
US6335565B1 (en) 1996-12-04 2002-01-01 Hitachi, Ltd. Semiconductor device
US6611012B2 (en) 1996-12-04 2003-08-26 Hitachi, Ltd. Semiconductor device
US7138722B2 (en) 1996-12-04 2006-11-21 Renesas Technology Corp. Semiconductor device
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US6630731B2 (en) 1999-07-30 2003-10-07 Hitachi, Ltd. Semiconductor device
US6900074B2 (en) 1999-07-30 2005-05-31 Renesas Technology Corp. Method of manufacturing a semiconductor device having plural semiconductor chips, wherein electrodes of the semiconductor chips are electrically connected together via wiring substrates of the semiconductor chips

Also Published As

Publication number Publication date
JP2631665B2 (en) 1997-07-16

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees