JPS6480884A - Scan path constituting method - Google Patents
Scan path constituting methodInfo
- Publication number
- JPS6480884A JPS6480884A JP62237332A JP23733287A JPS6480884A JP S6480884 A JPS6480884 A JP S6480884A JP 62237332 A JP62237332 A JP 62237332A JP 23733287 A JP23733287 A JP 23733287A JP S6480884 A JPS6480884 A JP S6480884A
- Authority
- JP
- Japan
- Prior art keywords
- scan path
- test pattern
- circuit
- generation
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To generate a test pattern efficiency and test a logic circuit by dividing the circuit advantageously to the generation of the test pattern and then constituting a scan path. CONSTITUTION:Input connection data 101 having no scan path is divided into plural partial circuits by circuit division 102 and the scan path is constituted 104 according to the division information 103 to generate connection data 105 including the scan path. The arrangement of the circuit, the layout 106 of wiring, etc., and the generation 108 of the test pattern are performed by using the data and layout data 107 and test pattern 109 are generated with them. Thus, the scan path constitution is performed after the advantageous circuit division for the generation of the test pattern to improve the generation efficiency of the test pattern, thereby shortening the measurement time of an actual circuit test.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62237332A JPS6480884A (en) | 1987-09-24 | 1987-09-24 | Scan path constituting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62237332A JPS6480884A (en) | 1987-09-24 | 1987-09-24 | Scan path constituting method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6480884A true JPS6480884A (en) | 1989-03-27 |
Family
ID=17013809
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62237332A Pending JPS6480884A (en) | 1987-09-24 | 1987-09-24 | Scan path constituting method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6480884A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6415404B1 (en) | 1998-09-10 | 2002-07-02 | Nec Corporation | Method of an apparatus for designing test facile semiconductor integrated circuit |
US6681356B1 (en) | 2000-09-29 | 2004-01-20 | International Business Machines Corporation | Scan chain connectivity |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5556261A (en) * | 1978-10-20 | 1980-04-24 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Testing method for sequential circuit |
JPS56140448A (en) * | 1980-04-03 | 1981-11-02 | Nec Corp | Logical operation circuit |
JPS6199875A (en) * | 1984-10-23 | 1986-05-17 | Toshiba Corp | Scan system logical circuit |
JPS61155874A (en) * | 1984-12-28 | 1986-07-15 | Toshiba Corp | Method and device for detecting fault of large-scale integrated circuit |
JPS6293672A (en) * | 1985-10-21 | 1987-04-30 | Hitachi Ltd | Hierarchy type logical apparatus |
JPS62124470A (en) * | 1985-11-26 | 1987-06-05 | Hitachi Ltd | Diagnosing method for logic circuit |
-
1987
- 1987-09-24 JP JP62237332A patent/JPS6480884A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5556261A (en) * | 1978-10-20 | 1980-04-24 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Testing method for sequential circuit |
JPS56140448A (en) * | 1980-04-03 | 1981-11-02 | Nec Corp | Logical operation circuit |
JPS6199875A (en) * | 1984-10-23 | 1986-05-17 | Toshiba Corp | Scan system logical circuit |
JPS61155874A (en) * | 1984-12-28 | 1986-07-15 | Toshiba Corp | Method and device for detecting fault of large-scale integrated circuit |
JPS6293672A (en) * | 1985-10-21 | 1987-04-30 | Hitachi Ltd | Hierarchy type logical apparatus |
JPS62124470A (en) * | 1985-11-26 | 1987-06-05 | Hitachi Ltd | Diagnosing method for logic circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6415404B1 (en) | 1998-09-10 | 2002-07-02 | Nec Corporation | Method of an apparatus for designing test facile semiconductor integrated circuit |
US6681356B1 (en) | 2000-09-29 | 2004-01-20 | International Business Machines Corporation | Scan chain connectivity |
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