JPS6416974A - Test data generating method - Google Patents

Test data generating method

Info

Publication number
JPS6416974A
JPS6416974A JP62172333A JP17233387A JPS6416974A JP S6416974 A JPS6416974 A JP S6416974A JP 62172333 A JP62172333 A JP 62172333A JP 17233387 A JP17233387 A JP 17233387A JP S6416974 A JPS6416974 A JP S6416974A
Authority
JP
Japan
Prior art keywords
expression
circuit
fault
logical
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62172333A
Other languages
Japanese (ja)
Inventor
Takahiro Honda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62172333A priority Critical patent/JPS6416974A/en
Publication of JPS6416974A publication Critical patent/JPS6416974A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To improve the efficiency and performance of the automatic generation of test data by setting logical expressions of a normal circuit and a circuit assumed to be faulty respectively and converting them to the forms of the sums of the minimum AND. CONSTITUTION:For example, the logic table of the logic circuit to be tested which is supplied from a design data file 11 is retrieved to generate the logical expression 51 of the normal circuit. Then a fault table is generated according to a data file 11 as to input/output terminals of respective logic elements constituting the logic circuit to be tested, and one assumed fault is selected in this fault table to generate the logical expression 52 of the logic circuit with a fixed fault. Those logical expressions 51 and 52 are converted to the forms of the sum of the minimum AND. For example, when the number of input terminals of the logical expression constituting the logic circuit is three, the expression is converted to the form of the sum of three-input AND. Consequently, when there is a common term between the two logical expressions, the terminal is deleted from the expression of the sum of the minimum AND as a term which generates an ineffective pattern. Then when there remaining terms, test patterns are generated for the respective terms.
JP62172333A 1987-07-10 1987-07-10 Test data generating method Pending JPS6416974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62172333A JPS6416974A (en) 1987-07-10 1987-07-10 Test data generating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62172333A JPS6416974A (en) 1987-07-10 1987-07-10 Test data generating method

Publications (1)

Publication Number Publication Date
JPS6416974A true JPS6416974A (en) 1989-01-20

Family

ID=15939956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62172333A Pending JPS6416974A (en) 1987-07-10 1987-07-10 Test data generating method

Country Status (1)

Country Link
JP (1) JPS6416974A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006126027A (en) * 2004-10-29 2006-05-18 System Jd:Kk Extraction method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006126027A (en) * 2004-10-29 2006-05-18 System Jd:Kk Extraction method

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