JPS647643A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS647643A JPS647643A JP62161252A JP16125287A JPS647643A JP S647643 A JPS647643 A JP S647643A JP 62161252 A JP62161252 A JP 62161252A JP 16125287 A JP16125287 A JP 16125287A JP S647643 A JPS647643 A JP S647643A
- Authority
- JP
- Japan
- Prior art keywords
- base
- resin
- cap
- refuse
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
PURPOSE:To prevent the lowering of the reliability of a semiconductor device due to refuse and dust intruding into a package by coating the internal surfaces of a base and a cap for the package with a resin attracting refuse, dust, etc. CONSTITUTION:In a semiconductor device hermetically sealing a semiconductor element chip 3 loaded onto a base 1 for a package by a cap 6, etc., the internal surfaces of the base 1 and the cap 6 are coated with a resin 8 attracting X such as refuse, dust. The semiconductor element chip 3 is bonded with a cavity 2 formed to the top face of the base 1 such as a ceramic base 1, and the semiconductor element chip 3 and a lead frame 4 are electrically connected by bonding wires 5. The base 1 is covered with a ceramics cap 6, and the base 1 and the cap 6 are hermetically sealed with low-melting-point glass 7. The rear of the ceramic cap 6 is coated with the resin 8 at that time, and a resin generating static electricity on the surface after thermosetting is used as the resin 8. A polyimide resin, a silicone resin, etc., are employed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62161252A JPS647643A (en) | 1987-06-30 | 1987-06-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62161252A JPS647643A (en) | 1987-06-30 | 1987-06-30 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS647643A true JPS647643A (en) | 1989-01-11 |
Family
ID=15731553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62161252A Pending JPS647643A (en) | 1987-06-30 | 1987-06-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS647643A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0310544U (en) * | 1989-06-15 | 1991-01-31 | ||
JP2007266195A (en) * | 2006-03-28 | 2007-10-11 | Dainippon Printing Co Ltd | Multilayer printed-wiring board and manufacturing method therefor |
JP2009038363A (en) * | 2007-07-09 | 2009-02-19 | Panasonic Corp | Rigid flexible printed circuit board, and its manufacturing method |
-
1987
- 1987-06-30 JP JP62161252A patent/JPS647643A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0310544U (en) * | 1989-06-15 | 1991-01-31 | ||
JP2007266195A (en) * | 2006-03-28 | 2007-10-11 | Dainippon Printing Co Ltd | Multilayer printed-wiring board and manufacturing method therefor |
JP2009038363A (en) * | 2007-07-09 | 2009-02-19 | Panasonic Corp | Rigid flexible printed circuit board, and its manufacturing method |
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