JPS6444051A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6444051A JPS6444051A JP62199711A JP19971187A JPS6444051A JP S6444051 A JPS6444051 A JP S6444051A JP 62199711 A JP62199711 A JP 62199711A JP 19971187 A JP19971187 A JP 19971187A JP S6444051 A JPS6444051 A JP S6444051A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- substrate
- resin
- forming
- flowing out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
PURPOSE:To reduce the cost of a semiconductor device by composing a frame for preventing resin from flowing out of paste-like substance formed on a substrate. CONSTITUTION:A semiconductor chip 2 for forming an LSI is placed on a flat substrate 1 in which its surface is formed, for example, of glass epoxy or triazine. A frame 5 made, for example, of silicon rubber paste for preventing resin from flowing out is provided on the substrate 1, has, for example, a triangular sectional shape, and the chip 2 and wirings 3 are sealed with resin 6, such as epoxy resin in the frame 5. When the frame 5 for preventing the resin from flowing out is composed of the paste in this manner, works of mechanical working and bonding for forming the frame 5 are eliminated. Further, since the substrate 1 having a flat surface is employed, a working for forming a cavity is obviated. Thus, the substrate 1 becomes inexpensive, and hence the cost of the package can be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62199711A JPS6444051A (en) | 1987-08-12 | 1987-08-12 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62199711A JPS6444051A (en) | 1987-08-12 | 1987-08-12 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6444051A true JPS6444051A (en) | 1989-02-16 |
Family
ID=16412338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62199711A Pending JPS6444051A (en) | 1987-08-12 | 1987-08-12 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6444051A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0340458A (en) * | 1989-07-07 | 1991-02-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
US5866941A (en) * | 1995-02-23 | 1999-02-02 | Silicon Systems, Inc. | Ultra thin, leadless and molded surface mount integrated circuit package |
KR100564542B1 (en) * | 1999-02-01 | 2006-03-28 | 삼성전자주식회사 | Chip scale package &method for fabrication thereof |
JP2010245128A (en) * | 2009-04-01 | 2010-10-28 | Showa Denko Kk | Method of forming resin object, method of manufacturing light emitting body, resin object forming apparatus, and light emitting body manufacturing apparatus |
EP2492957A3 (en) * | 2011-02-22 | 2012-11-07 | SEMIKRON Elektronik GmbH & Co. KG | Switching assembly |
-
1987
- 1987-08-12 JP JP62199711A patent/JPS6444051A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0340458A (en) * | 1989-07-07 | 1991-02-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
US5866941A (en) * | 1995-02-23 | 1999-02-02 | Silicon Systems, Inc. | Ultra thin, leadless and molded surface mount integrated circuit package |
KR100564542B1 (en) * | 1999-02-01 | 2006-03-28 | 삼성전자주식회사 | Chip scale package &method for fabrication thereof |
JP2010245128A (en) * | 2009-04-01 | 2010-10-28 | Showa Denko Kk | Method of forming resin object, method of manufacturing light emitting body, resin object forming apparatus, and light emitting body manufacturing apparatus |
EP2492957A3 (en) * | 2011-02-22 | 2012-11-07 | SEMIKRON Elektronik GmbH & Co. KG | Switching assembly |
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