JPS647534A - System of connecting integrated circuit device for testing - Google Patents

System of connecting integrated circuit device for testing

Info

Publication number
JPS647534A
JPS647534A JP62163731A JP16373187A JPS647534A JP S647534 A JPS647534 A JP S647534A JP 62163731 A JP62163731 A JP 62163731A JP 16373187 A JP16373187 A JP 16373187A JP S647534 A JPS647534 A JP S647534A
Authority
JP
Japan
Prior art keywords
input
output pads
test
circuit blocks
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62163731A
Other languages
Japanese (ja)
Inventor
Kiyoshi Takemori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62163731A priority Critical patent/JPS647534A/en
Publication of JPS647534A publication Critical patent/JPS647534A/en
Pending legal-status Critical Current

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Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To make it possible to analyze the failure analysis at the time of trouble separating special functional circuit blocks from the other circuits by a method wherein input/output pads for test for testing the special functional circuit blocks in the interior of a chip are provided in the interior of the chip separately from input/output pads for external connection to correspond to the probes of probe cards. CONSTITUTION:Input/output interface parts of special functional circuit blocks 3-1 and 3-2 are each provided with input/output pads for test 5-1 and 5-2, probe cards of an LSI tester are also provided with probes in such a way as to correspond to these input/output pads and those probes are brought into contact to the input/output pads for test to be connected. Moreover, even though circuit blocks equivalent to the circuit blocks 3-1 and 3-2 exist a plurality, the input/ output pads for test can be similarly provided without being restricted by the number of input/output pads for external connection. The input/output pads for test 5-1 and 5-2 have only to be provided at the minimum input/output parts only needed for testing the circuit blocks 3-1 and 3-2. Thereby, the resetting of test conditions becomes unnecessary.
JP62163731A 1987-06-29 1987-06-29 System of connecting integrated circuit device for testing Pending JPS647534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62163731A JPS647534A (en) 1987-06-29 1987-06-29 System of connecting integrated circuit device for testing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62163731A JPS647534A (en) 1987-06-29 1987-06-29 System of connecting integrated circuit device for testing

Publications (1)

Publication Number Publication Date
JPS647534A true JPS647534A (en) 1989-01-11

Family

ID=15779595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62163731A Pending JPS647534A (en) 1987-06-29 1987-06-29 System of connecting integrated circuit device for testing

Country Status (1)

Country Link
JP (1) JPS647534A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486686B1 (en) 1999-10-29 2002-11-26 Nec Corporation Apparatus for testing a bare-chip LSI mounting on a printed board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486686B1 (en) 1999-10-29 2002-11-26 Nec Corporation Apparatus for testing a bare-chip LSI mounting on a printed board

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