JPS6468868A - Buffer control system for bus adapter - Google Patents

Buffer control system for bus adapter

Info

Publication number
JPS6468868A
JPS6468868A JP62227116A JP22711687A JPS6468868A JP S6468868 A JPS6468868 A JP S6468868A JP 62227116 A JP62227116 A JP 62227116A JP 22711687 A JP22711687 A JP 22711687A JP S6468868 A JPS6468868 A JP S6468868A
Authority
JP
Japan
Prior art keywords
address
buffer memory
memory
case
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62227116A
Other languages
Japanese (ja)
Inventor
Kenichi Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62227116A priority Critical patent/JPS6468868A/en
Publication of JPS6468868A publication Critical patent/JPS6468868A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To apparently enable quick service to continuous DMA read requests from an input/output device by generating the next address by an adder to fetch data into a buffer memory in case of a hit at the time of accessing the buffer memory by a DMA read request address. CONSTITUTION:When the buffer memory is accessed by the memory read request address from a second common bus 100', data in this address is transferred to input/output devices 41-45 in case of a hit. In case of a hit during the memory read request of input/output devices 41-45, one or -1 is added to the address to access the buffer memory again; and in case of a mishit as the result, memory read is requested to a main memory 20 by the added address to fetch response data from the main memory 20 into the buffer memory. This buffer memory consists of a register 15, an address RAM 13, a data RAM 14, an adder 16, a comparator 17, a register 12, and a gate circuit 18. Thus, high speed buffering is possible.
JP62227116A 1987-09-09 1987-09-09 Buffer control system for bus adapter Pending JPS6468868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62227116A JPS6468868A (en) 1987-09-09 1987-09-09 Buffer control system for bus adapter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62227116A JPS6468868A (en) 1987-09-09 1987-09-09 Buffer control system for bus adapter

Publications (1)

Publication Number Publication Date
JPS6468868A true JPS6468868A (en) 1989-03-14

Family

ID=16855728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62227116A Pending JPS6468868A (en) 1987-09-09 1987-09-09 Buffer control system for bus adapter

Country Status (1)

Country Link
JP (1) JPS6468868A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0844659A (en) * 1994-07-27 1996-02-16 Nec Corp Data transfer controller
JPH08147236A (en) * 1994-11-18 1996-06-07 Nec Corp Transfer controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0844659A (en) * 1994-07-27 1996-02-16 Nec Corp Data transfer controller
JPH08147236A (en) * 1994-11-18 1996-06-07 Nec Corp Transfer controller

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