JPS6466950A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS6466950A JPS6466950A JP22465387A JP22465387A JPS6466950A JP S6466950 A JPS6466950 A JP S6466950A JP 22465387 A JP22465387 A JP 22465387A JP 22465387 A JP22465387 A JP 22465387A JP S6466950 A JPS6466950 A JP S6466950A
- Authority
- JP
- Japan
- Prior art keywords
- output buffer
- input
- blocks
- semiconductor chip
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 abstract 4
- 230000010354 integration Effects 0.000 abstract 2
- 230000003467 diminishing effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
PURPOSE:To scale down a semiconductor chip, and to improve the degree of integration by forming input/output buffer blocks having maximum driving capacity to an L shape in an integrated circuit device having a logic section block formed at a central section on the semiconductor chip and a plurality of input/output buffer blocks having the same function and different driving capacity on the chip of the outer circumference of the logical section block. CONSTITUTION:Input/output buffer blocks 6, 7 respectively have the same driving capacity as input/output buffer blocks 3b, but the blocks 6, 7 are formed to an L shape. Consequently, the depth of an input/output buffer block array shaped along one side of a semiconductor chip 1 can be reduced. Accordingly, a logic section block 2a on the inside can be made wider than conventional logic section blocks 2, thus diminishing a dead space, then improving the degree of integration. That is, a semiconductor chip can be scaled down to an integrated circuit device in the Same LSI scale.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62224653A JPH0760855B2 (en) | 1987-09-07 | 1987-09-07 | Integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62224653A JPH0760855B2 (en) | 1987-09-07 | 1987-09-07 | Integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6466950A true JPS6466950A (en) | 1989-03-13 |
JPH0760855B2 JPH0760855B2 (en) | 1995-06-28 |
Family
ID=16817095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62224653A Expired - Lifetime JPH0760855B2 (en) | 1987-09-07 | 1987-09-07 | Integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0760855B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5437755A (en) * | 1993-01-12 | 1995-08-01 | Salomon S.A. | Process for decorating the top portion of the ski |
US5777354A (en) * | 1994-09-16 | 1998-07-07 | Lsi Logic Corporation | Low profile variable width input/output cells |
US5917207A (en) * | 1993-07-01 | 1999-06-29 | Lsi Logic Corporation | Programmable polysilicon gate array base cell architecture |
US5945696A (en) * | 1998-02-16 | 1999-08-31 | Faraday Technology Corp. | Silicon chip having mixed input/output slot structure |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57139954A (en) * | 1981-02-24 | 1982-08-30 | Nec Corp | Master-sliced large scale integrated circuit |
JPS62154640A (en) * | 1985-12-26 | 1987-07-09 | Nec Corp | Semiconductor device |
-
1987
- 1987-09-07 JP JP62224653A patent/JPH0760855B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57139954A (en) * | 1981-02-24 | 1982-08-30 | Nec Corp | Master-sliced large scale integrated circuit |
JPS62154640A (en) * | 1985-12-26 | 1987-07-09 | Nec Corp | Semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5437755A (en) * | 1993-01-12 | 1995-08-01 | Salomon S.A. | Process for decorating the top portion of the ski |
US5917207A (en) * | 1993-07-01 | 1999-06-29 | Lsi Logic Corporation | Programmable polysilicon gate array base cell architecture |
US5777354A (en) * | 1994-09-16 | 1998-07-07 | Lsi Logic Corporation | Low profile variable width input/output cells |
US5945696A (en) * | 1998-02-16 | 1999-08-31 | Faraday Technology Corp. | Silicon chip having mixed input/output slot structure |
Also Published As
Publication number | Publication date |
---|---|
JPH0760855B2 (en) | 1995-06-28 |
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