JPS6461854A - Co-processor controller - Google Patents

Co-processor controller

Info

Publication number
JPS6461854A
JPS6461854A JP21857287A JP21857287A JPS6461854A JP S6461854 A JPS6461854 A JP S6461854A JP 21857287 A JP21857287 A JP 21857287A JP 21857287 A JP21857287 A JP 21857287A JP S6461854 A JPS6461854 A JP S6461854A
Authority
JP
Japan
Prior art keywords
information
processor
bus
processors
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21857287A
Other languages
Japanese (ja)
Inventor
Jiro Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP21857287A priority Critical patent/JPS6461854A/en
Publication of JPS6461854A publication Critical patent/JPS6461854A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To minimize the time required for exchange of information between processors by securing the free accesses of a main processor to all registers set into a co-processor. CONSTITUTION:A main processor 1 contains an address bus 11 and an information bus 12 and processes the information on a processing system. A co-processor 2 exclusively takes charge of the host arithmetic processing and contains a CPU 21 and a memory 22. The CPU 21 includes an accumulator 211, a stack memory 212, a program counter 213 which stores the address of the instruction to be executed next, and another register 214. An address bus 23 and an information bus 24 are connected to the co-processor 2. Thus the processor 1 can freely have accesses to all registers via the buffers 13 and 14. In such a constitution, the information transfer time is minimized between processors and the information can be easily processed.
JP21857287A 1987-09-01 1987-09-01 Co-processor controller Pending JPS6461854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21857287A JPS6461854A (en) 1987-09-01 1987-09-01 Co-processor controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21857287A JPS6461854A (en) 1987-09-01 1987-09-01 Co-processor controller

Publications (1)

Publication Number Publication Date
JPS6461854A true JPS6461854A (en) 1989-03-08

Family

ID=16722047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21857287A Pending JPS6461854A (en) 1987-09-01 1987-09-01 Co-processor controller

Country Status (1)

Country Link
JP (1) JPS6461854A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5723926A (en) * 1995-04-25 1998-03-03 Minebea Co., Ltd. Stepping motor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5723926A (en) * 1995-04-25 1998-03-03 Minebea Co., Ltd. Stepping motor

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