JPS6455854A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6455854A
JPS6455854A JP62213307A JP21330787A JPS6455854A JP S6455854 A JPS6455854 A JP S6455854A JP 62213307 A JP62213307 A JP 62213307A JP 21330787 A JP21330787 A JP 21330787A JP S6455854 A JPS6455854 A JP S6455854A
Authority
JP
Japan
Prior art keywords
circuit
terminal
input terminal
enable signal
latch circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62213307A
Other languages
Japanese (ja)
Inventor
Isao Takimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62213307A priority Critical patent/JPS6455854A/en
Publication of JPS6455854A publication Critical patent/JPS6455854A/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To make a semiconductor integrated circuit multifunctional including the function of inspection without increasing the number of terminals by installing thereto a circuit having several functions as well as an operation mode control circuit for such functions, and using an input terminal of the operation mode control circuit as an input terminal of the circuit of a certain function. CONSTITUTION:Invertor circuits 2a and 2b are so formed that the logical threshold for the invertor circuit 2a is smaller than that for the invertor circuit 2b. A P-type MOS transistor 3 is connected to an input terminal of a latch circuit 5, and a drain terminal of the P-type MOS transistor 3 is connected to an output terminal of the latch circuit 5. The input terminal of the latch circuit 5 is connected to a terminal C2 which sends an enable signal C to a circuit within an area shown by one dot chain line, and the output terminal of the latch circuit 5 is connected to a terminal C1 which sends an enable signal C. At the time of turning the power on, the input terminal of the latch circuit 5 is at the low level, while the output terminal thereof the high level. Accordingly, the enable signal C is on H level while the enable signal C1 is at the low level, whereby the circuit within the area shown by one-dot-chain line is in the normal operation mode.
JP62213307A 1987-08-27 1987-08-27 Semiconductor integrated circuit device Pending JPS6455854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62213307A JPS6455854A (en) 1987-08-27 1987-08-27 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62213307A JPS6455854A (en) 1987-08-27 1987-08-27 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6455854A true JPS6455854A (en) 1989-03-02

Family

ID=16636964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62213307A Pending JPS6455854A (en) 1987-08-27 1987-08-27 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6455854A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009257897A (en) * 2008-04-16 2009-11-05 Mitsumi Electric Co Ltd Semiconductor integrated circuit with built-in timer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009257897A (en) * 2008-04-16 2009-11-05 Mitsumi Electric Co Ltd Semiconductor integrated circuit with built-in timer

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