JPS6446974A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6446974A JPS6446974A JP62203771A JP20377187A JPS6446974A JP S6446974 A JPS6446974 A JP S6446974A JP 62203771 A JP62203771 A JP 62203771A JP 20377187 A JP20377187 A JP 20377187A JP S6446974 A JPS6446974 A JP S6446974A
- Authority
- JP
- Japan
- Prior art keywords
- region
- sidewall
- diffusion
- diffusion region
- low concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To give each low concentration diffusion region a symmetrical property with respect to a gate electrode, stabilize device chracteristics, and simplify a manufacture process, by a method wherein arsenic is selectively ion-implanted on a semiconductor substrate by using the gate electrode and a sidewall for masks and a heat-treatment is performed. CONSTITUTION:Since each low concentration N<-> diffusion region is formed by diffusion of phosphorus P from a sidewall 18 of a PSG film formed on the gate oxide film 16 and the sidewall of a gate electrode 17, each region can be formed in perfectly symmetrical positions, and device characteristics are stabilized thereby. After the formation of the sidewall 18 of the PSG film and the selective ion-implantation of arsenic As, each low concentration N<-> diffusion region is formed by only one-time heat-treatment, and each high concentration N<+> diffusion region turning to a source-drain region is formed by diffusion of arsenic As implanted at the same time. Thereby, the manufacturing process of each low concentration N<-> diffusion region and each high concentration region mentioned above can be simplified.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62203771A JPS6446974A (en) | 1987-08-17 | 1987-08-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62203771A JPS6446974A (en) | 1987-08-17 | 1987-08-17 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6446974A true JPS6446974A (en) | 1989-02-21 |
Family
ID=16479535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62203771A Pending JPS6446974A (en) | 1987-08-17 | 1987-08-17 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6446974A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5302195A (en) * | 1991-05-22 | 1994-04-12 | Xerox Corporation | Ink compositions containing cyclodextrins |
US5913116A (en) * | 1997-01-08 | 1999-06-15 | Advanced Micro Devices | Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer |
-
1987
- 1987-08-17 JP JP62203771A patent/JPS6446974A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5302195A (en) * | 1991-05-22 | 1994-04-12 | Xerox Corporation | Ink compositions containing cyclodextrins |
US5913116A (en) * | 1997-01-08 | 1999-06-15 | Advanced Micro Devices | Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer |
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