JPS6444723U - - Google Patents
Info
- Publication number
- JPS6444723U JPS6444723U JP13919387U JP13919387U JPS6444723U JP S6444723 U JPS6444723 U JP S6444723U JP 13919387 U JP13919387 U JP 13919387U JP 13919387 U JP13919387 U JP 13919387U JP S6444723 U JPS6444723 U JP S6444723U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- collectors
- whose
- transistor
- reference potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第1図はこの考案に係るフリツプフロツプ回路
の一実施例を示す回路構成図、第2図は従来のフ
リツプフロツプ回路を示す回路構成図である。
11……電源端子、12,13……出力端子、
14……入力端子、15……電源端子、16,1
7……出力端子、18……入力端子。
FIG. 1 is a circuit diagram showing an embodiment of a flip-flop circuit according to this invention, and FIG. 2 is a circuit diagram showing a conventional flip-flop circuit. 11...Power terminal, 12,13...Output terminal,
14...Input terminal, 15...Power terminal, 16,1
7...Output terminal, 18...Input terminal.
Claims (1)
のベース〜コレクタ同志が接続された第1及び第
2のトランジスタと、この第1及び第2のトラン
ジスタのコレクタと第1の基準電位点との間にそ
れぞれ介挿接続された第1及び第2の抵抗と、前
記第1及び第2のトランジスタのベースにそれぞ
れのエミツタが接続され互いのベース〜コレクタ
同志が接続された第3及び第4のトランジスタと
、この第3及び第4のトランジスタの互いのベー
ス〜コレクタ同志の接続点間に直列に介挿接続さ
れた第3及び第4の抵抗と、この第3及び第4の
抵抗同志の接続点にコレクタが接続されエミツタ
が第2の基準電位点に接続された第5のトランジ
スタと、前記第1及び第2のトランジスタのエミ
ツタ共通接続点と前記第2の基準電位点との間に
介挿接続された第5の抵抗とを具備し、前記第1
、第2及び第5のトランジスタと前記第3及び第
4のトランジスタとをそれぞれ異なる極性とし、
前記第5のトランジスタのベースを入力端とする
とともに、前記第1及び第2のトランジスタのコ
レクタをそれぞれ第1及び第2の出力端とするよ
うに構成してなることを特徴とするフリツプフロ
ツプ回路。 first and second transistors whose emitters are commonly connected and whose bases and collectors are connected; and between the collectors of the first and second transistors and a first reference potential point, respectively. first and second resistors interposed and connected; third and fourth transistors whose emitters are connected to the bases of the first and second transistors, and whose bases and collectors are connected to each other; A third and a fourth resistor are connected in series between the base and the collector of the third and fourth transistors, and a collector is connected to the connection point between the third and fourth resistors. a fifth transistor whose emitter is connected to the second reference potential point, and a fifth transistor which is interposed and connected between the emitter common connection point of the first and second transistors and the second reference potential point. a fifth resistor;
, the second and fifth transistors and the third and fourth transistors have different polarities,
A flip-flop circuit characterized in that the base of the fifth transistor is used as an input terminal, and the collectors of the first and second transistors are used as first and second output terminals, respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13919387U JPS6444723U (en) | 1987-09-11 | 1987-09-11 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13919387U JPS6444723U (en) | 1987-09-11 | 1987-09-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6444723U true JPS6444723U (en) | 1989-03-17 |
Family
ID=31402224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13919387U Pending JPS6444723U (en) | 1987-09-11 | 1987-09-11 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6444723U (en) |
-
1987
- 1987-09-11 JP JP13919387U patent/JPS6444723U/ja active Pending