JPS6423574A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6423574A JPS6423574A JP17899387A JP17899387A JPS6423574A JP S6423574 A JPS6423574 A JP S6423574A JP 17899387 A JP17899387 A JP 17899387A JP 17899387 A JP17899387 A JP 17899387A JP S6423574 A JPS6423574 A JP S6423574A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- resist
- buried
- piled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To fine an LSI and to realize high reliability in electrode wiring, by piling a gate electrode material film and successively forming a film in thickness that is larger than a width of an inclined region of a groove formed in the gate electrode material film existing on the substrate. CONSTITUTION:After a polycrystalline silicon film for gate electrode 13' is piled, a film 17 of oxide or nitride or the like is piled in thickness d2 which is equal to or larger than width d1 of an inclined region of a side wall of a groove 21 formed inside an opening part 65. This film 17 is coated with a resist thickly to perform etch back so that a resist film 3 is buried into the groove 21. Next this buried resist film 3 is used as a mask to etch the film 17 with high precision. After the polycrystalline silicon 13' is etched successively, the resist film 3 is removed. The surface of the polycrystalline silicon film 13 for gate electrode is oxidized to form an oxide film 14, and next source/drain diffusion layers 11, 12 are formed, and the oxide film is removed by etching to expose silicon on an upper part of the diffusion layer and to make a tungsten film 18 grow selectively. An interlayer film 15 is buried into grooves on both sides, end its piled surface is flattened. Accordingly disconnection can be prevented so as to realize fining in LSI and high reliability in electrode wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62178993A JP2531688B2 (en) | 1987-07-20 | 1987-07-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62178993A JP2531688B2 (en) | 1987-07-20 | 1987-07-20 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6423574A true JPS6423574A (en) | 1989-01-26 |
JP2531688B2 JP2531688B2 (en) | 1996-09-04 |
Family
ID=16058238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62178993A Expired - Fee Related JP2531688B2 (en) | 1987-07-20 | 1987-07-20 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2531688B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006261307A (en) * | 2005-03-16 | 2006-09-28 | Toshiba Corp | Pattern forming method |
-
1987
- 1987-07-20 JP JP62178993A patent/JP2531688B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006261307A (en) * | 2005-03-16 | 2006-09-28 | Toshiba Corp | Pattern forming method |
Also Published As
Publication number | Publication date |
---|---|
JP2531688B2 (en) | 1996-09-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4758530A (en) | Doubly-self-aligned hole-within-a-hole structure in semiconductor fabrication involving a double LOCOS process aligned with sidewall spacers | |
US6821858B2 (en) | Semiconductor devices and methods for manufacturing the same | |
US6579764B2 (en) | Integrated circuit memory devices having non-volatile memory transistors and methods of fabricating the same | |
JPS61198780A (en) | Manufacture of semiconductor device | |
US5369052A (en) | Method of forming dual field oxide isolation | |
GB1517242A (en) | Integrated circuits | |
JPS55153377A (en) | Production of semiconductor device | |
JPS60160653A (en) | Manufacture of semiconductor device | |
JPS5842251A (en) | Manufacture of semiconductor device | |
JPS54108582A (en) | Manufacture of silicon type field effect transistor | |
JPS61247051A (en) | Manufacture of semiconductor device | |
JPS6423574A (en) | Manufacture of semiconductor device | |
US5523605A (en) | Semiconductor device and method for forming the same | |
JPS6457717A (en) | Manufacture of semiconductor device | |
JPS61228650A (en) | Manufacture of semiconductor device | |
JPS5583267A (en) | Method of fabricating semiconductor device | |
JPS6428962A (en) | Semiconductor device and manufacture thereof | |
JPS60105247A (en) | Manufacture of semiconductor device | |
JPS6453559A (en) | Manufacture of semiconductor device | |
JPS5447489A (en) | Production of mos semiconductor device | |
JPS56126957A (en) | Manufacture of semiconductor device | |
JPS6428923A (en) | Formation of taper-shaped trench | |
JPS6468965A (en) | Manufacture of semiconductor device | |
JPH0230160A (en) | Semiconductor device | |
KR960026221A (en) | Semiconductor device manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |