JPS6423574A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6423574A
JPS6423574A JP17899387A JP17899387A JPS6423574A JP S6423574 A JPS6423574 A JP S6423574A JP 17899387 A JP17899387 A JP 17899387A JP 17899387 A JP17899387 A JP 17899387A JP S6423574 A JPS6423574 A JP S6423574A
Authority
JP
Japan
Prior art keywords
film
gate electrode
resist
buried
piled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17899387A
Other languages
Japanese (ja)
Other versions
JP2531688B2 (en
Inventor
Toshio Kobayashi
Hiroshi Inokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62178993A priority Critical patent/JP2531688B2/en
Publication of JPS6423574A publication Critical patent/JPS6423574A/en
Application granted granted Critical
Publication of JP2531688B2 publication Critical patent/JP2531688B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To fine an LSI and to realize high reliability in electrode wiring, by piling a gate electrode material film and successively forming a film in thickness that is larger than a width of an inclined region of a groove formed in the gate electrode material film existing on the substrate. CONSTITUTION:After a polycrystalline silicon film for gate electrode 13' is piled, a film 17 of oxide or nitride or the like is piled in thickness d2 which is equal to or larger than width d1 of an inclined region of a side wall of a groove 21 formed inside an opening part 65. This film 17 is coated with a resist thickly to perform etch back so that a resist film 3 is buried into the groove 21. Next this buried resist film 3 is used as a mask to etch the film 17 with high precision. After the polycrystalline silicon 13' is etched successively, the resist film 3 is removed. The surface of the polycrystalline silicon film 13 for gate electrode is oxidized to form an oxide film 14, and next source/drain diffusion layers 11, 12 are formed, and the oxide film is removed by etching to expose silicon on an upper part of the diffusion layer and to make a tungsten film 18 grow selectively. An interlayer film 15 is buried into grooves on both sides, end its piled surface is flattened. Accordingly disconnection can be prevented so as to realize fining in LSI and high reliability in electrode wiring.
JP62178993A 1987-07-20 1987-07-20 Method for manufacturing semiconductor device Expired - Fee Related JP2531688B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62178993A JP2531688B2 (en) 1987-07-20 1987-07-20 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62178993A JP2531688B2 (en) 1987-07-20 1987-07-20 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6423574A true JPS6423574A (en) 1989-01-26
JP2531688B2 JP2531688B2 (en) 1996-09-04

Family

ID=16058238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62178993A Expired - Fee Related JP2531688B2 (en) 1987-07-20 1987-07-20 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2531688B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006261307A (en) * 2005-03-16 2006-09-28 Toshiba Corp Pattern forming method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006261307A (en) * 2005-03-16 2006-09-28 Toshiba Corp Pattern forming method

Also Published As

Publication number Publication date
JP2531688B2 (en) 1996-09-04

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees