JPS6419826A - Digital pll circuit - Google Patents
Digital pll circuitInfo
- Publication number
- JPS6419826A JPS6419826A JP62175732A JP17573287A JPS6419826A JP S6419826 A JPS6419826 A JP S6419826A JP 62175732 A JP62175732 A JP 62175732A JP 17573287 A JP17573287 A JP 17573287A JP S6419826 A JPS6419826 A JP S6419826A
- Authority
- JP
- Japan
- Prior art keywords
- output clock
- frequency
- counter
- long
- cycle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To substantially enhance arithmetic accuracy for a PLL operation to N times and to prevent the deterioration of response speed by counting the cycle approximately N times as long as an output clock pulse. CONSTITUTION:The output clock CKOUT (frequency fOUT) from an output clock generating circuit part 20 is sent to the N/K-ary counter 31 of a cycle data detecting circuit 30, the pulse output of the frequency of N/K times as long as the frequency fOUT is obtained and sent to the clear terminal CL of a counter 32. Latch circuits 33-36 latch the four successive counted values of count outputs sequentially outputted with a period N.TOUT/4 from the counter 32 to be a cycle. The outputs of these latches are added in a four input adder 37 and output clock cycle data is obtained by multiplying by 1/N. Thereby, an adverse influence such as a long pulling-in time to the clock frequency or the deterioration of the response speed can be avoided even when N is increased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62175732A JPS6419826A (en) | 1987-07-14 | 1987-07-14 | Digital pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62175732A JPS6419826A (en) | 1987-07-14 | 1987-07-14 | Digital pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6419826A true JPS6419826A (en) | 1989-01-23 |
Family
ID=16001271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62175732A Pending JPS6419826A (en) | 1987-07-14 | 1987-07-14 | Digital pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6419826A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0588656A2 (en) * | 1992-09-18 | 1994-03-23 | Sony Corporation | Digital PLL circuit having signal edge position measurement |
| US6366150B1 (en) | 1997-05-23 | 2002-04-02 | Mitsubishi Denki Kabushiki Kaisha | Digital delay line |
-
1987
- 1987-07-14 JP JP62175732A patent/JPS6419826A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0588656A2 (en) * | 1992-09-18 | 1994-03-23 | Sony Corporation | Digital PLL circuit having signal edge position measurement |
| EP0588656A3 (en) * | 1992-09-18 | 1994-06-01 | Sony Corp | Digital pll circuit having signal edge position measurement |
| US6366150B1 (en) | 1997-05-23 | 2002-04-02 | Mitsubishi Denki Kabushiki Kaisha | Digital delay line |
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