JPS5472647A - Synchronous processing system for multiple logical device - Google Patents

Synchronous processing system for multiple logical device

Info

Publication number
JPS5472647A
JPS5472647A JP13967577A JP13967577A JPS5472647A JP S5472647 A JPS5472647 A JP S5472647A JP 13967577 A JP13967577 A JP 13967577A JP 13967577 A JP13967577 A JP 13967577A JP S5472647 A JPS5472647 A JP S5472647A
Authority
JP
Japan
Prior art keywords
circuit
constituted
gate
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13967577A
Other languages
Japanese (ja)
Inventor
Tadao Kawamura
Kunio Nagasaki
Fumio Wada
Tatsuhiro Saito
Kohei Takanashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JAPANESE NATIONAL RAILWAYS<JNR>
Nippon Signal Co Ltd
Japan National Railways
Original Assignee
JAPANESE NATIONAL RAILWAYS<JNR>
Nippon Signal Co Ltd
Japan National Railways
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JAPANESE NATIONAL RAILWAYS<JNR>, Nippon Signal Co Ltd, Japan National Railways filed Critical JAPANESE NATIONAL RAILWAYS<JNR>
Priority to JP13967577A priority Critical patent/JPS5472647A/en
Publication of JPS5472647A publication Critical patent/JPS5472647A/en
Pending legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Information Transfer Systems (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE: To enable to perform succeeding synchronous operation completely by correcting othe difference of delay and advance of generation of a receiving completion signal in the receiving portion by the use of a majority circuit.
CONSTITUTION: Receiving completion detecting portion MPA (surrounded by a solid line) including majority circuit 40 is equipped in synchronous portion PC. In addition, the synchronous processing circuit of the triple logical device includes receivind portions R1 to R3, processing portions T1 to T3 and output portions S1 to S3. Moreover, MPA is constituted by FF1 to FF3 that store temporally receiving completion signals from each system according to each system, 2 input and gates G1P to G3P, 3 input "or" gate G5P (majority circuit 40 is constituted by combination of each gate), bynary counter CuP, decoder DECP that converts binary digit into decimal digit, 2 input and gate G4P, and inverter IV (counting circuit 50 is constituted by th units). Thus, when output q of circuit 40 is generated, counter 50 is advanced in every generation of clock pulse CP and, when the counting value of DECP reaches j, output rp is generated.
COPYRIGHT: (C)1979,JPO&Japio
JP13967577A 1977-11-21 1977-11-21 Synchronous processing system for multiple logical device Pending JPS5472647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13967577A JPS5472647A (en) 1977-11-21 1977-11-21 Synchronous processing system for multiple logical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13967577A JPS5472647A (en) 1977-11-21 1977-11-21 Synchronous processing system for multiple logical device

Publications (1)

Publication Number Publication Date
JPS5472647A true JPS5472647A (en) 1979-06-11

Family

ID=15250792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13967577A Pending JPS5472647A (en) 1977-11-21 1977-11-21 Synchronous processing system for multiple logical device

Country Status (1)

Country Link
JP (1) JPS5472647A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5769403A (en) * 1980-10-16 1982-04-28 Toshiba Corp Doubled device for sequence control
JPS57146303A (en) * 1981-03-06 1982-09-09 Toshiba Corp Synchronizing method for multiplex computer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5769403A (en) * 1980-10-16 1982-04-28 Toshiba Corp Doubled device for sequence control
JPS57146303A (en) * 1981-03-06 1982-09-09 Toshiba Corp Synchronizing method for multiplex computer system

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