JPS6415821A - 3-state control system - Google Patents

3-state control system

Info

Publication number
JPS6415821A
JPS6415821A JP62172217A JP17221787A JPS6415821A JP S6415821 A JPS6415821 A JP S6415821A JP 62172217 A JP62172217 A JP 62172217A JP 17221787 A JP17221787 A JP 17221787A JP S6415821 A JPS6415821 A JP S6415821A
Authority
JP
Japan
Prior art keywords
circuit
terminal
state control
constitution
inverted logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62172217A
Other languages
Japanese (ja)
Inventor
Kazuo Azegami
Naohiro Masunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62172217A priority Critical patent/JPS6415821A/en
Publication of JPS6415821A publication Critical patent/JPS6415821A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To ensure the stable 3-state control with simple circuit constitution by setting a non-inverted logic circuit between two inverted logic circuits and setting a high impedance after an output is set at a high level. CONSTITUTION:Both inverted circuits 1 and 2 have the same circuit constitution. A signal B is supplied to the circuit 2 and the output terminal 2-4 of the circuit 2 is set at '0'. Under such conditions, the 3-state control signal A of the circuit 1 is set at '1' and therefore the output terminal 1-4 of the circuit 1 is set at '0'. Then a current flows to a diode D3. As a result, the terminal 2-4 is set at '1'. At the same time, '0' of the terminal 1-4 is supplied to a non-inverted logic circuit 3 and the terminal 3-4 of the circuit 3 is set at '1' to cut off the current flowing to a diode D6. Thus the terminal 2-4 has a high impedance.
JP62172217A 1987-07-09 1987-07-09 3-state control system Pending JPS6415821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62172217A JPS6415821A (en) 1987-07-09 1987-07-09 3-state control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62172217A JPS6415821A (en) 1987-07-09 1987-07-09 3-state control system

Publications (1)

Publication Number Publication Date
JPS6415821A true JPS6415821A (en) 1989-01-19

Family

ID=15937765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62172217A Pending JPS6415821A (en) 1987-07-09 1987-07-09 3-state control system

Country Status (1)

Country Link
JP (1) JPS6415821A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179371A (en) * 1987-08-13 1993-01-12 Seiko Epson Corporation Liquid crystal display device for reducing unevenness of display
US5202676A (en) * 1988-08-15 1993-04-13 Seiko Epson Corporation Circuit for driving a liquid crystal display device and method for driving thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179371A (en) * 1987-08-13 1993-01-12 Seiko Epson Corporation Liquid crystal display device for reducing unevenness of display
US5202676A (en) * 1988-08-15 1993-04-13 Seiko Epson Corporation Circuit for driving a liquid crystal display device and method for driving thereof

Similar Documents

Publication Publication Date Title
JPS6429018A (en) Input protection device for semiconductor circuit device
JPS5573994A (en) Three-state output circuit
JPS6415821A (en) 3-state control system
JPS5750139A (en) Hysteresis circuit
JPS57162838A (en) Emitter coupling type logical circuit
JPS5735422A (en) Semiconductor circuit
JPS56119530A (en) Semiconductor integrated circuit
JPS5535574A (en) Logic device
JPS56107641A (en) Semiconductor circuit equipment
JPS5779457A (en) Voltage comparing circuit
JPS57101430A (en) Termination resistor chip provided with tie-up means
JPS56140686A (en) Pockels' cell driving circuit
JPS6435496A (en) High sound volume bell circuit
JPS5768929A (en) Flip-flop circuit
JPS5733832A (en) Output circuit
JPS6412708A (en) Bi-directional signal selection circuit
JPS5558813A (en) Input circuit for selection signal
JPS566537A (en) Input circuit
JPS57154938A (en) Input recognizing circuit
JPS6439119A (en) Logical operation circuit
JPS55151806A (en) Signal level control circuit
JPS57162833A (en) Pulse generator
JPS5791057A (en) Connecting device for communication line
JPS6410726A (en) Bus potential hold circuit
JPS5541020A (en) Logic output circuit