JPS6386924A - Original exponent-vector converting circuit on galois body - Google Patents
Original exponent-vector converting circuit on galois bodyInfo
- Publication number
- JPS6386924A JPS6386924A JP61232003A JP23200386A JPS6386924A JP S6386924 A JPS6386924 A JP S6386924A JP 61232003 A JP61232003 A JP 61232003A JP 23200386 A JP23200386 A JP 23200386A JP S6386924 A JPS6386924 A JP S6386924A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- outputted
- alphan
- exponent
- vector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 14
- 239000000126 substance Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 1
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- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はデジタル処理回路に関し、特にその符号化・復
号回路において用いられるガロア体（ｇａＩＬｏｉｓ体
：加減乗除の四則演算が行える元の集合で元の数が有限
であるもの。通常、ｑを元の数としてＧＦ（ｑ）で表わ
す。）上の元の指数・ベクトル変換回路に関する。Detailed Description of the Invention (Industrial Application Field) The present invention relates to digital processing circuits, and in particular to a Galois field (gaILois field), which is a set of elements that can perform four arithmetic operations such as addition, subtraction, multiplication, and division. (usually expressed as GF(q), where q is the number of elements).
従来、ガロア体上の元の指数・ベクトル変換は処理が非
常に複雑であるので、指数・ベクトル変換回路としては
ＲＯＭ （リードオンメモリー）に指数−ベクトル対応
テーブルを生成しておきそれにより変換処理を行なうの
が通常であった。Conventionally, the exponent/vector conversion of the original on the Galois field is very complicated, so the exponent/vector conversion circuit generates an exponent/vector correspondence table in ROM (read-on memory) and performs the conversion process using that table. It was usual to do so.
しかしながらＲＯＭは回路構成が大きいので回路構成の
簡略化には不適であった。このためＲＯＭに変わる簡差
で回路量の小さい指数・ベクトル変換回路が望まれてい
た。However, ROM has a large circuit configuration and is therefore unsuitable for simplifying the circuit configuration. For this reason, there has been a desire for an index/vector conversion circuit that is simple to replace the ROM and has a small amount of circuitry.
Ｃ問題点を解決するための手段）
本発明は、ＲＯＭを用いず、ゲート回路及び乗算回路に
よってガロア体上の元の指数・ベクトル変換を行なう簡
単な回路の指数・ベクトル変換回路を提供することを目
的とする。Means for Solving Problem C) The present invention provides a simple exponent/vector conversion circuit that performs exponent/vector conversion of an element on a Galois field using a gate circuit and a multiplication circuit without using a ROM. With the goal.
以下、本発明の実施例について説明する。 Examples of the present invention will be described below.
指数・ベクトル変換回路においては指数ｎはバイナリで
入力され、次のように表される。In the exponent/vector conversion circuit, the exponent n is input in binary and is expressed as follows.
それからαｎを生成するために次のように分解される。It is then decomposed as follows to generate αn.
ｎ＝Ｎ７・１２Ｂ＋Ｎ８・６４＋Ｎ５・３２＋Ｎ４・１
６＋Ｎ３・８＋Ｎ２・４＋Ｎ１・２＋ＮＯ・１
α０＝αＮ？、１２ａ・αＮ６°６４ ・αＮ５−３
２ ・αＮ４・１６− ａ Ｎ ３°ａ 、 ａ Ｎ
２°４・αＮ１−２・αＮ。n=N7・12B+N8・64+N5・32+N4・1
6+N3・8+N2・4+N1・2+NO・1 α0=αN? , 12a・αN6°64・αN5-3
2 ・αN4・16- a N 3°a, a N
2°4・αN1−2・αN.
従って、Ｎｉ （ｉ＝ｏ・・・７）が１のときα２“１
を出力し、０のとき１を出力する回路を構成し、その出
力を順次束じていけばよい。そのブロック図を第１図に
示し、その動作タイミングを第２図に示す。符号長ｎの
バイナリ−表現がＮＯ→Ｎ７の順で送られてきたときパ
スラインＹにはαＮＯ−αＮ？弓２８が出力され乗算回
路２に送られる。乗算回路２の出力Ｚからは順次αＮ０
〜αＮ？弓２１１を乗じた出力が出力される。その出力
をレジスタ３にとりこみ、乗算回路２のもう一つの入力
端子Ｘに出力する。ただし、Ｘには、最初ＹがαＮ０を
出力した時１を出力するようにレジスタの内容をセット
しておく。αＮ７°１２６が出力されたときα０が生成
される。Therefore, when Ni (i=o...7) is 1, α2"1
It is sufficient to construct a circuit that outputs 1 when the value is 0, and then sequentially bundles the outputs. Its block diagram is shown in FIG. 1, and its operation timing is shown in FIG. When a binary representation of code length n is sent in the order NO→N7, the path line Y has αNO−αN? The bow 28 is output and sent to the multiplication circuit 2. From the output Z of the multiplier circuit 2, αN0
~αN? The output multiplied by the bow 211 is output. The output is taken into the register 3 and outputted to the other input terminal X of the multiplication circuit 2. However, the contents of the register are set in X so that 1 is output when Y first outputs αN0. When αN7°126 is output, α0 is generated.
ＨＣＫは、ＮＯ〜Ｎ７が出力されている間図示しないク
ロック発振器から出力されているクロックパルスである
。HCK is a clock pulse that is output from a clock oscillator (not shown) while NO to N7 are being output.
ここでＮＯ〜Ｎフに従ってαＮ０〜Ｎ７弓２６を出力す
る指数／ベクトル回路１の構成を第３図に示す。FIG. 3 shows the configuration of the index/vector circuit 1 which outputs the αN0 to N7 bows 26 according to NO to N.
この回路は従来はＲＯＭによって生成されていたが本実
施例ではゲート回路によって構成しである。尚、第３図
において口はＥｘｃｌｕｓｉｖｅ ＯＲ（排他的論理
和）回路、＋はパスラインを示す。第３図の回路は既約
多項式がｐ （ｘ）”ｘ’ ＋ｘ４ ＋ｘ３ ＋ｘ”
＋１の場合においてＮ ｉ ＝ １ （ｉ ＝Ｏ→７
） （Ｄとき順次ａ＝（０１０ｏｏｏｏｏ）、 α”
＝ （００１０００００）。Conventionally, this circuit was generated by a ROM, but in this embodiment, it is constructed by a gate circuit. In FIG. 3, the opening indicates an exclusive OR (exclusive OR) circuit, and the symbol + indicates a pass line. In the circuit of Figure 3, the irreducible polynomial is p (x)"x' +x4 +x3 +x"
+1, N i = 1 (i = O → 7
) (When D, sequentially a=(010oooooo), α”
= (00100000).
ａ’ ＝ （００００１０００）、ａａ−（１０１１１
０００）、ａ′６＝（００１１００１０）、ａ”＝（１
０１１１００１）、ａ６４＝（１１１１１０１０）、ａ
”’ ＝ （ｔｏｔｏｏｏｏｔ）を出力し、Ｎ１＝０の
とき１を出力するゲート回路構成になっている。a' = (00001000), aa-(10111
000), a′6=(00110010), a”=(1
0111001), a64=(11111010), a
The gate circuit has a configuration that outputs ``' = (totoooot) and outputs 1 when N1=0.
以上の構成によって、指数表現ｎから、ベクトル表現α
０への変換を簡略化されたゲート回路と乗算回路によっ
て行なうことができる。With the above configuration, from the exponential representation n, the vector representation α
Conversion to 0 can be performed by simplified gate circuits and multiplier circuits.
第１ 図（Ｄ 例ではα０生成までにＮｏＮＮ７をシリ
アルに出力するために８クロツク入カ必要であるが、ク
ロック入力数を少なくしたい場合ＮＯ〜Ｎ７をパラレル
に出力し、乗算回路をそれに応じて複数もっことによっ
てクロック人力にすることもできる。その場合回路量が
多少本実施例より多くなる。Figure 1 (D) In the example, 8 clock inputs are required to serially output NoNN7 by the time α0 is generated, but if you want to reduce the number of clock inputs, output NO~N7 in parallel and adjust the multiplication circuit accordingly. The clock can also be manually operated by using a plurality of clocks.In that case, the amount of circuitry will be somewhat larger than in this embodiment.
以上説明したように、本発明の指数・ベクトル変換回路
はゲート回路及び乗算回路によって構成したので小さい
回路量で指数・ベクトル変換を行なうことができるとい
う効果を奏する。As explained above, since the exponent/vector conversion circuit of the present invention is constituted by a gate circuit and a multiplication circuit, it has the advantage of being able to perform exponent/vector conversion with a small amount of circuitry.
第１図は本発明の実施例に係る指数・ベクトル変換回路
のブロック図、第２図は第１図のブロック図の動作タイ
ミングチャート、第３図は指数／ベクトル回路の構成を
示す図である。
１ −−−−−一指数／ベクトル回路
２ −−−一−−乗算回路
３−−−−−−レジスタFIG. 1 is a block diagram of an index/vector conversion circuit according to an embodiment of the present invention, FIG. 2 is an operation timing chart of the block diagram of FIG. 1, and FIG. 3 is a diagram showing the configuration of the index/vector circuit. . 1 ----1 index/vector circuit 2 ----1 multiplication circuit 3 -------Register
Claims (1)
・Ｎ＿ｍ＿−＿２＋・・・＋２・Ｎ＿１＋Ｎ＿０ のＮｉ（ｉ＝０・・・ｍ−１）＝１に対応して▲数式、
化学式、表等があります▼を出力し、Ｎｉ＝０に対応し
て１を 出力する回路手段と、該回路手段の出力を順次乗算する
乗算回路とから構成され、ｎのベクトル表現 ▲数式、化学式、表等があります▼ を生成出力することを特徴としたガロア体上の元の指数
・ベクトル変換回路。[Claims] Binary representation of original index on Galois field GF(2^m) n=2^m^-^1・N_m_-_1+2^m^-^2
・Corresponding to Ni (i=0...m-1)=1 of N_m_-_2+...+2・N_1+N_0 ▲ Formula,
It consists of a circuit means that outputs ▼ and outputs 1 in response to Ni=0, and a multiplier circuit that sequentially multiplies the output of the circuit means, and a vector representation of n ▲ Mathematical formula, chemical formula , tables, etc. ▼ An original exponent/vector conversion circuit on a Galois field, which is characterized by generating and outputting .
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61232003A JPH0783277B2 (en) | 1986-09-30 | 1986-09-30 | Original representation format conversion circuit on Galois field |
| DE3752367T DE3752367T2 (en) | 1986-09-30 | 1987-09-29 | Error correction unit |
| DE3751958T DE3751958T2 (en) | 1986-09-30 | 1987-09-29 | Error correction device |
| EP87308648A EP0262944B1 (en) | 1986-09-30 | 1987-09-29 | Error correction apparatus |
| EP96200874A EP0723342B1 (en) | 1986-09-30 | 1987-09-29 | Error correction apparatus |
| EP93201798A EP0566215B1 (en) | 1986-09-30 | 1987-09-29 | Error correction apparatus |
| DE3789266T DE3789266T2 (en) | 1986-09-30 | 1987-09-29 | Error correction device. |
| US08/400,521 US5590138A (en) | 1986-09-30 | 1995-03-07 | Error correction apparatus |
| US08/701,327 US5774389A (en) | 1986-09-30 | 1996-08-23 | Error correction apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61232003A JPH0783277B2 (en) | 1986-09-30 | 1986-09-30 | Original representation format conversion circuit on Galois field |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6386924A true JPS6386924A (en) | 1988-04-18 |
| JPH0783277B2 JPH0783277B2 (en) | 1995-09-06 |
Family
ID=16932418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61232003A Expired - Fee Related JPH0783277B2 (en) | 1986-09-30 | 1986-09-30 | Original representation format conversion circuit on Galois field |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783277B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012205272A (en) * | 2011-03-28 | 2012-10-22 | Toshiba Corp | Reed-solomon decoder and reception apparatus |
-
1986
- 1986-09-30 JP JP61232003A patent/JPH0783277B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012205272A (en) * | 2011-03-28 | 2012-10-22 | Toshiba Corp | Reed-solomon decoder and reception apparatus |
| US9077382B2 (en) | 2011-03-28 | 2015-07-07 | Kabushiki Kaisha Toshiba | Reed-solomon decoder and reception apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0783277B2 (en) | 1995-09-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |