JPS6376380A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6376380A JPS6376380A JP22038486A JP22038486A JPS6376380A JP S6376380 A JPS6376380 A JP S6376380A JP 22038486 A JP22038486 A JP 22038486A JP 22038486 A JP22038486 A JP 22038486A JP S6376380 A JPS6376380 A JP S6376380A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- mobility
- gaas layer
- stripes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000012535 impurity Substances 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 24
- 238000013139 quantization Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000013459 approach Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000007789 gas Substances 0.000 abstract 2
- 125000005842 heteroatom Chemical group 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 20
- 239000010931 gold Substances 0.000 description 7
- 230000005533 two-dimensional electron gas Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 230000005669 field effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
この発明は、空間分離ドーピングと界面量子化による電
子ガスをチャネルとする電界効果トランジスタにかかり
、
チャネル領域のヘテロ接合界面を複数の相互に平行なス
トライプ状に成形して、ストライプ相互間で分離された
１次元量子化に準する電子ガスを生成することにより、
電子の移動度を高めて、半導体装置の高速化を進めるも
のである。[Detailed Description of the Invention] [Summary] The present invention relates to a field effect transistor that uses an electron gas as a channel by spatially separated doping and interface quantization, and in which the heterojunction interface in the channel region is formed into a plurality of mutually parallel stripes. By molding and producing an electron gas that corresponds to one-dimensional quantization separated between stripes, the mobility of electrons is increased and the speed of semiconductor devices is increased.
本発明は半導体装置、特に空間分離ドーピングと界面量
子化による１次元に準する高移動度の電子ガスをチャネ
ルとする半導体装置に関する。The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a channel is a high-mobility electron gas based on one-dimensional doping and interface quantization.
従来知られている高電子移動度電界効果トランジスタ（
ＨＥＭＴ）は２次元量子化された電子ガスをチャネルと
しているが、この２次元量子化状態を１次元量子化状態
に近づけた更に高電子移動度の半導体装置の実現が要望
されている。The conventionally known high electron mobility field effect transistor (
HEMT) uses a two-dimensional quantized electron gas as a channel, but there is a desire to realize a semiconductor device with even higher electron mobility in which the two-dimensional quantized state approaches the one-dimensional quantized state.
従来のＨＥＭＴの一例の模式側断面図を第３図に示す。 A schematic side sectional view of an example of a conventional HEMT is shown in FIG.
本従来例では半絶縁性砒化ガリウム（ＧａＡｓ）基板２
１上に、ノンドープのｉ形ＧａＡｓ層２２と、これより
電子親和力が小さく例えば濃度２×１０１１１ＣＩ＋１
弓程度にドナー不純物がドープされたｎ型砒化アルミニ
ウムガリウム（ＡＩＸＧａｌ−ＸＭＳ）層２３と、これ
と同程度以上にドナー不純物がドープされたｎ型ＧａＡ
ｓ層２４とが設けられ、ｎ型ＡｌＧａＡｓ１Ｊ２３から
ｉ形ＧａＡｓ層２２へ遷移した電子によってヘテロ接合
界面近傍に２次元電子ガス２２ｅが形成される。In this conventional example, a semi-insulating gallium arsenide (GaAs) substrate 2
1, there is a non-doped i-type GaAs layer 22 on top of the undoped i-type GaAs layer 22, and a layer 22 having a smaller electron affinity than that, for example, a concentration of 2×10111CI+1.
An n-type aluminum gallium arsenide (AIXGal-XMS) layer 23 doped with donor impurities to the extent of an arch, and an n-type GaA layer 23 doped with donor impurities to the same extent or more.
A two-dimensional electron gas 22e is formed near the heterojunction interface by electrons transferred from the n-type AlGaAs1J23 to the i-type GaAs layer 22.
この半導体基体のｎ型ＧａＡｓ層２４上に例えば金ゲル
マニウム／金（ＡｕＧｅ／Ａｕ）を用いてソース、ドレ
イン電極２６を設け、ｎ型ＡｌＧａＡｓ電子供給層２３
上に例えばチタン／白金／金（Ｔｉ／Ｐｔ／Ａｕ）又は
アルミニウム（ＡＩ）等を用いてゲート電極２７を設け
る。なお２６Ａはソース、ドレイン電極２６と半導体基
体との間に形成された合金化領域である。Source and drain electrodes 26 are provided on the n-type GaAs layer 24 of this semiconductor substrate using, for example, gold germanium/gold (AuGe/Au), and the n-type AlGaAs electron supply layer 23
A gate electrode 27 is provided thereon using, for example, titanium/platinum/gold (Ti/Pt/Au) or aluminum (AI). Note that 26A is an alloyed region formed between the source/drain electrode 26 and the semiconductor substrate.
ゲート電極２７によるショットキ空乏層で２次元電子ガ
ス２２ｅの面密度を制御してトランジスタ動作が行われ
るが、この２次元電子ガス２２ｅは不純物散乱による移
動度低下が殆どなく、格子散乱が低下する例えば７７に
程度以下の低温において最も高い移動度が得られる。こ
の場合の電子移動度は通常１〜１０Ｘ１０’ｃｍ”／Ｖ
、ｓ、例えば６ Ｘ １０’ｃｍ”／Ｖ、ｓ程度であり
、不純物をドープしたＧａＡｓ単結晶内の電子移動度が
Ｉ Ｘ １０’ｃｍ”／Ｖ、ｓ以下であるのに比較すれ
ば遥かに高い値が得られている。Transistor operation is performed by controlling the areal density of the two-dimensional electron gas 22e in the Schottky depletion layer formed by the gate electrode 27, but this two-dimensional electron gas 22e has almost no reduction in mobility due to impurity scattering and, for example, when lattice scattering is reduced. The highest mobility is obtained at low temperatures below 77°C. In this case, the electron mobility is usually 1 to 10×10'cm"/V
, s, for example, about 6 x 10'cm"/V, s, which is much lower than the electron mobility in a GaAs single crystal doped with impurities, which is less than I x 10'cm"/V, s. A high value has been obtained.
上述の様に、２次元電子ガスをチャネルとするＨＥＭＴ
は従来の電界効果トランジスタ中でキャリアの移動度が
最も高く、ゲート長の短縮と相俟って、半導体装置の高
速化の代表的な例となっている。As mentioned above, HEMT uses two-dimensional electron gas as a channel.
has the highest carrier mobility among conventional field effect transistors, and together with shortening the gate length, it has become a typical example of increasing the speed of semiconductor devices.
しかしながらパターンの微細化、ゲート長の短縮にも限
界があり、電子の１次元量子化或いはこれに準する状態
によってキャリア移動度を更に高めた電界効果トランジ
スタを具体的に実現することが要望されている。However, there are limits to miniaturization of patterns and shortening of gate length, and there is a need to concretely realize field-effect transistors that further increase carrier mobility through one-dimensional quantization of electrons or a similar state. There is.
前記問題点は、ノンドープの第１の半導体層と、該第１
の半導体層より電子親和力が小さくドナー不純物を含む
第２の半導体層とのヘテロ接合を備え、
チャネル領域の該ヘテロ接合界面が複数の相互に平行な
ストライプ状に成形されて、該ストライプ相互間で分離
され、かつ少なくとも該界面に垂直方向について量子化
された電子ガスが該界面近傍に生成され、
該ストライプに交差して配設されたゲート電極により該
電子ガスを制御する本発明による半導体装置により解決
される。The problem is that the non-doped first semiconductor layer and the first
The channel region has a heterojunction with a second semiconductor layer that has a smaller electron affinity than the second semiconductor layer and contains donor impurities, and the heterojunction interface of the channel region is formed into a plurality of mutually parallel stripes, and there are gaps between the stripes. By the semiconductor device according to the present invention, an electron gas that is separated and quantized at least in a direction perpendicular to the interface is generated near the interface, and the electron gas is controlled by a gate electrode disposed intersecting the stripe. resolved.
本発明によれば、空間分離ドーピングされたヘテロ接合
界面のチャネル領域を、複数の相互に平行で幅が狭いス
トライプ状に成形し、該界面に垂直方向については従来
の２次元電子ガスと同様に量子化され、ストライプ幅方
向についてはストライプ相互間で分離され、量子化され
ないまでも１次元量子化に準する散乱作用が少ない電子
ガスを生成させて、その電子移動度を従来の２次元電子
ガスより高くする。According to the present invention, the channel region of the spatially separated doped heterojunction interface is formed into a plurality of mutually parallel narrow stripes, and the direction perpendicular to the interface is similar to the conventional two-dimensional electron gas. The electron gas is quantized and separated between stripes in the stripe width direction, and although it is not quantized, it generates an electron gas with a low scattering effect similar to one-dimensional quantization, and its electron mobility is compared to that of a conventional two-dimensional electron gas. make it higher.
１次元量子化に到達するためにはストライプの幅方向を
電子のドウ・ブロイ−波長（ＧａＡｓでは約３０ｎｍ）
以下にすることが必要であり、リソグラフィーエツチン
グ法等によるパターン形成でこれを実現することは困難
であるが、その１０倍程度以下として２次元電子ガスよ
り散乱作用を減少させ、移動度を増大することは可能で
ある。In order to achieve one-dimensional quantization, the width direction of the stripe must be aligned with the Doe-Brog wavelength of electrons (approximately 30 nm in GaAs).
Although it is difficult to achieve this by pattern formation using lithography etching methods, etc., it is necessary to reduce the scattering effect by about 10 times or less than the two-dimensional electron gas and increase the mobility. It is possible.
なおこの寸法にばらつきを生じてもゲート長短縮の場合
の様に特性が大幅に変動することはない。Note that even if variations occur in this dimension, the characteristics will not vary significantly as in the case of shortening the gate length.
更に複数のストライプが並列接続されるために、単に電
流を増大するのみでなく、ばらつきが平均化される効果
が得られている。Furthermore, since a plurality of stripes are connected in parallel, it is possible not only to simply increase the current but also to average out variations.
以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.
第１図は本発明の実施例の模式図であり、図（ａｌはそ
の平面図、図（ｂ）はＸ−Ｘ’断面図、図（Ｃ）はＹ−
Ｙ’断面図を示し、第２図（１１乃至（３）は本実施例
の製造工程中のＹ−Ｙ”断面図である。FIG. 1 is a schematic diagram of an embodiment of the present invention.
A Y' cross-sectional view is shown, and FIG. 2 (11 to (3)) is a Y-Y'' cross-sectional view during the manufacturing process of this embodiment.
図において、１は半絶縁性ＧａＡｓ基板、２は例えばシ
リコン（Ｓｔ）を濃度２ Ｘ １０１１＋ ａｍ−３程
度にドープしたｎ型Ａ１ｘＧａｔ−、Ａｓ（ｘ＝０．３
）層、３はノンドープのｉ型ＧａＡｓ層、４は例えばＳ
ｔを注入したｎ型ソース・ドレインコンタクト領域、５
は例えばＳｉｎｇからなる保護絶縁膜、６は例えばＡｕ
Ｇｅ／Ａｕからなるソース、ドレイン電極、６Ａはソー
ス、ドレイン電極６と半導体基体との間に形成された合
金化領域、７は例えばＡ１からなるゲート電極であり、
ｎ型ＡｔＧａＡｓ層２からｉ形ＧａＡｓ層３へ遷移した
電子によって、電子ガス３ｅがストライプ状にパターン
化された各ヘテロ接合界面近傍に形成されている。In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type A1x Gat-, As (x=0.3
) layer, 3 is a non-doped i-type GaAs layer, 4 is, for example, S
n-type source/drain contact region implanted with T, 5
6 is a protective insulating film made of, for example, Sing, and 6 is made of, for example, Au.
Source and drain electrodes made of Ge/Au; 6A is an alloyed region formed between the source and drain electrode 6 and the semiconductor substrate; 7 is a gate electrode made of, for example, A1;
Electrons transferred from the n-type AtGaAs layer 2 to the i-type GaAs layer 3 form an electron gas 3e in the vicinity of each heterojunction interface patterned into stripes.
本実施例は例えば下記の様に製造される。This example is manufactured, for example, as follows.
第２図（１）参照二 半絶縁性ＧａＡｓ基板１上に、例
えば分子線エピタキシャル成長方法により、前記ｎ型Ａ
ｌｘＧａ、−、Ａｓ層２とノンドープのｉ型ＧａＡｓ層
３とを、例えば厚さそれぞれ１１００ｎにエピタキシャ
ル成長する。Refer to FIG. 2 (1) 2. The n-type A
The lxGa, -, As layer 2 and the non-doped i-type GaAs layer 3 are epitaxially grown to a thickness of, for example, 1100 nm.
ｉ型ＧａＡｓ層３上に例えば５ｉＯｚ膜を設け、そのチ
ャネル領域上の部分に例えばマスク幅ｗＩ＝Ｑ、４ｇｍ
、開口幅ｗｚ＝Ｑ、４Ｉｎｎのストライプ状パターンを
形成して、マスク１１とする。For example, a 5iOz film is provided on the i-type GaAs layer 3, and a mask width wI=Q, 4gm is formed on the portion above the channel region.
, an opening width wz=Q, and a striped pattern of 4 Inn is formed to form a mask 11.
第２図（２）参照： このマスク１１を用いて、例えば
２塩化２弗化炭素（ＣＣｈＦｔ）によるリアクティブイ
オンエツチング法により、ｉ型ＧａＡｓ層３をエツチン
グする。このエツチング法ではＧａＡｓ層３がＡｌＧａ
Ａｓ層２に対して選択的にエツチングされ、サイドエツ
チング効果によりｉ型ＧａＡｓ層３をマスク幅Ｗ＋より
狭いストライプ幅Ｗ＝０．１〜０．２ｐｍ程度とする。Refer to FIG. 2(2): Using this mask 11, the i-type GaAs layer 3 is etched by, for example, a reactive ion etching method using carbon dichloride difluoride (CChFt). In this etching method, the GaAs layer 3 is made of AlGa
The As layer 2 is selectively etched, and the i-type GaAs layer 3 is made to have a stripe width W=0.1 to 0.2 pm, which is narrower than the mask width W+, due to the side etching effect.
第２図（３）参照： マスク１１を除去してＳｉｎｇ膜
５を堆積し、更にレジスト等の膜１２を被着してその上
表面を平坦にし、例えば４弗化炭素（ＣＦ４．）に酸素
（０２）を加えたドライエツチングにより、５ｉＯｚ膜
５間にｉ型ＧａＡｓ層３のストライプ状パターンが表出
する平坦面を形成する。Refer to FIG. 2 (3): The mask 11 is removed, the Sing film 5 is deposited, and a film 12 such as a resist is further applied to make the upper surface flat. By dry etching with (02) added, a flat surface is formed between the 5iOz films 5 on which the striped pattern of the i-type GaAs layer 3 is exposed.
第１図（ａｌ、（ｂ）参照： このエツチング処理によ
リソース・ドレインコンタクト領域４とするＧａＡｓ層
３も表出する。この領域のＧａＡｓ層３に、例えばＳｉ
をエネルギー１００ｋｅＶ程度でドーズ量１×１０１３
ＣＩｌ−２程度イオン注入し、活性化熱処理を行ってｎ
型ソース・ドレインコンタクト領域４を形成して、例え
ばＡｕＧｅ／Ａｕからなるソース、ドレイン電極６を配
設し、合金化熱処理を行う。Refer to FIGS. 1(al) and (b): Through this etching process, the GaAs layer 3 which will become the resource/drain contact region 4 is also exposed.
with an energy of about 100 keV and a dose of 1×1013
After implanting ions of CIl-2 and performing activation heat treatment,
Type source/drain contact regions 4 are formed, source and drain electrodes 6 made of, for example, AuGe/Au are provided, and alloying heat treatment is performed.
第１図（ａ）、（Ｃ）参照： 例えばＡ１からなるゲー
ト電極７を配設する。See FIGS. 1(a) and 1(C): A gate electrode 7 made of, for example, A1 is provided.
本実施例では例えば温度７７Ｋにおいて、電子移動度が
約Ｉ Ｘ １０６ｃｎ＋”／Ｖ、ｓであり、従来の２次
元量子化ＨＥＭＴの電子移動度が１〜１０ Ｘ １０’
ｃｍ”／Ｖ、ｓ、例えば６ Ｘ １０’ｃｍ”／Ｖ；ｓ
程度であるのに比較して、明らかな増大が実証されてい
る。In this embodiment, for example, at a temperature of 77 K, the electron mobility is about I x 106cn+"/V,s, and the electron mobility of a conventional two-dimensional quantized HEMT is 1 to 10 x 10'
cm"/V,s, e.g. 6 X 10'cm"/V;s
A clear increase has been demonstrated compared to the extent of
前記実施例ではｎ型ＡｌＧａＡｓ層を基板側としている
が、例えばノンドープのｉ型ＧａＡｓ層を基板側としｎ
型ＡｌＧａＡｓ層をその上に成長して、電子供給層をス
トライプ状にパターニングしても同様の効果を得ること
ができる。また本発明はＧａＡｓ／ＡｌＧａＡｓ系に限
られず、例えばＩｎＧａＡｓ ／ ＩｎＡｌＡｓ等を用
いた半導体装置に適用し得ることは明らかである。In the above embodiment, the n-type AlGaAs layer is on the substrate side, but for example, the non-doped i-type GaAs layer is on the substrate side.
A similar effect can be obtained by growing an AlGaAs layer thereon and patterning the electron supply layer into stripes. Furthermore, it is clear that the present invention is not limited to GaAs/AlGaAs semiconductor devices, but can be applied to semiconductor devices using, for example, InGaAs/InAlAs.
以上説明した如く本発明によれば、空間分離ドーピング
と１次元に準する界面量子化により、電子移動度が従来
のＨＥＭＴより更に増大されて半導体装置の高速化が一
層推進され、例えば次世代の電子計算システム等に大き
い効果を与える。As explained above, according to the present invention, the electron mobility is further increased than that of conventional HEMTs by spatially separated doping and interface quantization that approximates one-dimensionality, and the speeding up of semiconductor devices is further promoted. It has a great effect on electronic computing systems, etc.
第１図は本発明の実施例の模式図、
第２図はその製造工程中のＹ−Ｙ”断面図、第３図は従
来例の模式側断面図である。
図において、
１は半絶縁性ＧａＡｓ基板、
２はｎ型ＡｌｚＧａＩ−ｘＡｓ層、
３はノンドープのｉ型ＧａＡｓ層、
３ｅは電子ガス、
４はｎ型ソース・ドレインコンタクト領域、５は保護絶
縁膜、
６はソース、ドレイン電極、
６Ａは合金化領域、
７はゲート電極、
１１はマスク、
１２はレジスト等の膜を示す。
手１ 凶
票２ 図
従来ｆノ”１の漠式便層眉狛囚
＄３ ｇFig. 1 is a schematic diagram of an embodiment of the present invention, Fig. 2 is a cross-sectional view taken along the Y-Y” line during the manufacturing process, and Fig. 3 is a schematic side sectional view of a conventional example. 2 is an n-type AlzGaI-xAs layer, 3 is a non-doped i-type GaAs layer, 3e is an electron gas, 4 is an n-type source/drain contact region, 5 is a protective insulating film, 6 is a source and drain electrode, 6A is an alloyed region, 7 is a gate electrode, 11 is a mask, and 12 is a film such as a resist.
Claims (1)
電子親和力が小さくドナー不純物を含む第２の半導体層
とのヘテロ接合を備え、 チャネル領域の該ヘテロ接合界面が複数の相互に平行な
ストライプ状に成形されて、該ストライプ相互間で分離
され、かつ少なくとも該界面に垂直方向について量子化
された電子ガスが該界面近傍に生成され、 該ストライプに交差して配設されたゲート電極により該
電子ガスを制御することを特徴とする半導体装置。[Claims] A heterojunction is provided between a non-doped first semiconductor layer and a second semiconductor layer that has a smaller electron affinity than the first semiconductor layer and contains donor impurities, and the heterojunction interface in the channel region is Formed into a plurality of mutually parallel stripes, an electron gas separated between the stripes and quantized at least in a direction perpendicular to the interface is generated near the interface and distributed across the stripes. A semiconductor device characterized in that the electron gas is controlled by a gate electrode provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61220384A JPH07105490B2 (en) | 1986-09-18 | 1986-09-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61220384A JPH07105490B2 (en) | 1986-09-18 | 1986-09-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6376380A true JPS6376380A (en) | 1988-04-06 |
| JPH07105490B2 JPH07105490B2 (en) | 1995-11-13 |
Family
ID=16750277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61220384A Expired - Lifetime JPH07105490B2 (en) | 1986-09-18 | 1986-09-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07105490B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02134830A (en) * | 1988-11-15 | 1990-05-23 | Nec Corp | Field effect transistor |
| US6242765B1 (en) * | 1991-05-21 | 2001-06-05 | Nec Corporation | Field effect transistor and its manufacturing method |
| CN103383959A (en) * | 2013-07-04 | 2013-11-06 | 西安电子科技大学 | Crosswise overgrowth one-dimensional electron gas GaN-base high electron mobility transistor (HEMT) device and manufacturing method thereof |
| CN103400856A (en) * | 2013-07-04 | 2013-11-20 | 西安电子科技大学 | One-dimensional electronic gas GaN-based HEMT (High Electron Mobility Transistor) device adopting selective area epitaxy and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61170070A (en) * | 1985-01-23 | 1986-07-31 | Sony Corp | Semiconductor device |
-
1986
- 1986-09-18 JP JP61220384A patent/JPH07105490B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61170070A (en) * | 1985-01-23 | 1986-07-31 | Sony Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02134830A (en) * | 1988-11-15 | 1990-05-23 | Nec Corp | Field effect transistor |
| US6242765B1 (en) * | 1991-05-21 | 2001-06-05 | Nec Corporation | Field effect transistor and its manufacturing method |
| CN103383959A (en) * | 2013-07-04 | 2013-11-06 | 西安电子科技大学 | Crosswise overgrowth one-dimensional electron gas GaN-base high electron mobility transistor (HEMT) device and manufacturing method thereof |
| CN103400856A (en) * | 2013-07-04 | 2013-11-20 | 西安电子科技大学 | One-dimensional electronic gas GaN-based HEMT (High Electron Mobility Transistor) device adopting selective area epitaxy and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07105490B2 (en) | 1995-11-13 |
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