JPS63216379A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63216379A JPS63216379A JP5070887A JP5070887A JPS63216379A JP S63216379 A JPS63216379 A JP S63216379A JP 5070887 A JP5070887 A JP 5070887A JP 5070887 A JP5070887 A JP 5070887A JP S63216379 A JPS63216379 A JP S63216379A
- Authority
- JP
- Japan
- Prior art keywords
- carriers
- region
- interface
- channel
- stripe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000969 carrier Substances 0.000 claims abstract description 19
- 238000009826 distribution Methods 0.000 claims abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 10
- 125000005842 heteroatom Chemical group 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 13
- 239000007789 gas Substances 0.000 description 12
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- 238000013139 quantization Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000006251 one-dimensional electron gas Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
この発明は、
半導体層のヘテロ接合界面に平行で該界面を含むストラ
イプ状をなし、1次元に準する量子化状態のキャリアが
生成される領域をチャネルとし、その分岐点近傍に設け
られた電極でキャリアの伝導路を選択してスイッチング
動作を行うことにより・
半導体装置の高速化を推進するものである。[Detailed Description of the Invention] [Summary] The present invention provides a channel having a striped region parallel to and including the heterojunction interface of a semiconductor layer, in which carriers in a quantized state quasi-one-dimensional are generated. By selecting the carrier conduction path using an electrode provided near the branch point and performing a switching operation, the speed of semiconductor devices is promoted.
本発明は半導体装置、特に1次元或いはこれに準する状
態の高移動度のキャリアをチャネルとし、そのチャネル
を切り換えることによりスイッチング動作を行う新しい
半導体装置に関する。The present invention relates to a semiconductor device, and particularly to a new semiconductor device that uses high-mobility carriers in a one-dimensional or similar state as a channel and performs a switching operation by switching the channel.
従来知られている高電子移動度電界効果トランジスタ(
HEMT)は量子化により2次元状態とした電子ガスを
チャネルとしているが、この電子ガス等のキャリアを1
次元状態に近づけることにより、更に高い移動度で新し
い動作が行われる半導体装置が期待されている。The conventionally known high electron mobility field effect transistor (
HEMT) uses an electron gas made into a two-dimensional state by quantization as a channel, but the carriers of this electron gas are
By approaching the dimensional state, it is expected that semiconductor devices will be able to perform new operations with even higher mobility.
従来のI(EMTの一例の模式側断面図を第3図に示す
。本従来例では半絶縁性砒化ガリウム(GaAs)基F
i21上に、ノンドープのi形GaAs層22と、これ
より電子親和力が小さい高不純物濃度のn型砒化アルミ
ニウムガリウム(AlxGal−XAs)層23とが設
けられ、n型AlGaAs層23からi形GaAs層2
2へ遷移した電子によってヘテロ接合界面近傍に2次元
電子ガス24が形成される。A schematic side sectional view of an example of a conventional I (EMT) is shown in FIG. 3. In this conventional example, semi-insulating gallium arsenide (GaAs)
A non-doped i-type GaAs layer 22 and a highly impurity-concentrated n-type aluminum gallium arsenide (AlxGal-XAs) layer 23 having a lower electron affinity than the undoped i-type GaAs layer 21 are provided on the i21. 2
A two-dimensional electron gas 24 is formed near the heterojunction interface by the electrons that have transitioned to 2.
この半導体基体上に、ソース、ドレイン電極26.27
とゲート電極28とを設ける。ゲート電極28によるシ
ョットキ空乏層で2次元電子ガス24の面密度を制御し
てトランジスタ動作が行われるが、この2次元電子ガス
24は不純物散乱による移動度低下が殆どなく、格子散
乱が低下する例えば77に程度以下の低温におイテ、通
常L 〜10 X LO’cm2/V、s、例えば6
X 10’cm”/V、s程度の電子移動度が得られる
。この電子移動度は、不純物をドープしたGaAs単結
晶内の電子移動度がI X 10’cmF/V、s以下
であるのに比較してすれば大幅に高い値である。On this semiconductor substrate, source and drain electrodes 26 and 27 are provided.
and a gate electrode 28 are provided. Transistor operation is performed by controlling the areal density of the two-dimensional electron gas 24 in the Schottky depletion layer formed by the gate electrode 28, but this two-dimensional electron gas 24 has almost no reduction in mobility due to impurity scattering and, for example, when lattice scattering is reduced. It is used at a low temperature below 77°C, usually L ~ 10 x LO'cm2/V, s, e.g. 6
An electron mobility of approximately X 10'cm"/V,s can be obtained. This electron mobility is lower than the electron mobility in a GaAs single crystal doped with impurities, which is less than IX 10'cmF/V,s. This is a significantly higher value compared to .
上述の様に、2次元電子ガスをチャネルとするII E
M Tは従来の電界効果トランジスタ中でキャリアの
移動度が最も高(、ゲート長の短縮と相俟って半導体装
置の高速化の代表的な例となっている。As mentioned above, II E using two-dimensional electron gas as a channel
MT has the highest carrier mobility among conventional field effect transistors, and together with shortening of gate length, it is a typical example of increasing the speed of semiconductor devices.
しかしながらパターンの微細化、ゲート長の短縮にも限
界があり、1次元量子化或いはこれに準する状態によっ
てキャリア移動度を一層高め、更に新しい機能を持った
半導体装置を具体的に実現することが要望されている。However, there are limits to the miniaturization of patterns and shortening of gate length, and it is difficult to further increase carrier mobility through one-dimensional quantization or a state similar to this, and to concretely realize semiconductor devices with new functions. It is requested.
前記問題点は、半4体層のヘテロ接合界面に平行で該界
面を含むストライプ状の領域が設けられて、少なくとも
該界面に垂直方向について量子化されたキャリアが該領
域内に生成され、該領域の分岐点近傍に設けられた電極
により該キャリアの該界面に平行方向の分布を制御して
、該キャリアの伝導路を選択する本発明による半導体装
置により解決される。The problem is that a striped region parallel to and including the heterojunction interface of the semi-quadramid layer is provided, and carriers quantized at least in the direction perpendicular to the interface are generated in the region. This problem is solved by the semiconductor device of the present invention in which the distribution of the carriers in the direction parallel to the interface is controlled by an electrode provided near the branch point of the region to select the conduction path of the carriers.
本発明によれば、空間分離ドーピングされたヘテロ接合
界面のチャネル層を幅が狭いストライプ状に成形し、該
界面に垂直な方向については従来の2次元電子ガスと同
様に量子化され、ストライプ幅方向については量子化さ
れないまでも1次元量子化に準する散乱作用が少ないキ
ャリア、例えば電子ガスを生成させて、その移動度を従
来の2次元状態のキャリアより高くする。According to the present invention, the channel layer at the spatially separated doped heterojunction interface is formed into a narrow stripe shape, and in the direction perpendicular to the interface, it is quantized in the same way as a conventional two-dimensional electron gas, Even if the direction is not quantized, carriers with less scattering action similar to one-dimensional quantization, such as electron gas, are generated, and their mobility is made higher than that of conventional two-dimensional carriers.
1次元量子化に到達するためにはストライプの幅方向を
キャリアのドウ・ブロイ−波長(GaAsでは約30n
m)以下にすることが必要であり、リソグラフィーエツ
チング法等によるパターン形成でこれを実現することは
現在困難であるが、その10倍程度以下として2次元状
態より散乱作用を減少させ、移動度を増大することは可
能である。In order to achieve one-dimensional quantization, the width direction of the stripe must be aligned with the Doe-Brogj wavelength of the carrier (approximately 30 nm in GaAs).
m) or less, and it is currently difficult to achieve this by pattern formation using lithography etching methods, etc., but it is possible to reduce the scattering effect and increase the mobility by setting it to about 10 times or less than the two-dimensional state. It is possible to increase.
本発明では例えば第1図<8)に模式斜視図を示す実施
例の如く、この狭いストライプ状のチャネル領域5を5
へ、5Bに分岐し、その分岐点近傍に電極8A、8Bを
設ける。この半導体基体の断面X−X’のチャネル領域
5と断面Y−Y’のチャネル領域5A、5Bとのエネル
ギー準位及び電子ガス4の分布を、電極8A、 88間
に電圧を加えない場合について第1図(b)、電圧■。In the present invention, for example, as in the embodiment shown in the schematic perspective view in FIG.
5B, and electrodes 8A and 8B are provided near the branch point. The energy level and the distribution of electron gas 4 in the channel region 5 of the cross section XX' of this semiconductor substrate and the channel regions 5A and 5B of the cross section YY' are calculated for the case where no voltage is applied between the electrodes 8A and 88. Figure 1(b), voltage ■.
を加えた場合について同図(C1に示す。The same figure (shown in C1) shows the case where .
すなわち電極8A、8B間に電圧を加えない状態では同
図(b)に示す如く、電子ガス4のチャネル領域5内の
分布は左右均等で、分岐したチャネル領域5A、5Bに
均等に流入する。これに対して電極8A、8B間に電圧
■。を加えた状態では同図(C)に示す如く、電子ガス
4のチャネル領域5内の分布は5A側に集中し、分岐し
たチャネル領域5Aのみに流入する。That is, when no voltage is applied between the electrodes 8A and 8B, as shown in FIG. 2B, the distribution of the electron gas 4 within the channel region 5 is equal on the left and right sides, and it evenly flows into the branched channel regions 5A and 5B. On the other hand, the voltage ■ between electrodes 8A and 8B. In the state in which the electron gas 4 is added, the distribution of the electron gas 4 in the channel region 5 is concentrated on the 5A side, and flows only into the branched channel region 5A, as shown in FIG.
この様に分岐点において準1次元電子ガス4のチャネル
幅方向の分布を制御して、電子ガス4を伝4する分岐路
数、或いはどの分岐路に電子ガス4を伝導するかを選択
し、例えば抵抗体9に現れる電圧を出力として高速スイ
ッチング動作を実現する。In this way, by controlling the distribution of the quasi-one-dimensional electron gas 4 in the channel width direction at the branch point, the number of branch paths through which the electron gas 4 is transmitted, or which branch path the electron gas 4 is conducted to, is selected. For example, high-speed switching operation is realized by using the voltage appearing on the resistor 9 as an output.
〔実施例〕 以下本発明を実施例により具体的に説明する。〔Example〕 The present invention will be specifically explained below using examples.
第1図(alは本発明の実施例の模式斜視図、第1図(
b)、(C1はそれぞれ制御電圧vGを加えない場合と
加えた場合について、断面X−X’のチャネル領域5と
断面Y−Y’のチャネル領域5八、5Bとのエネルギー
準位及び電子ガス4の分布を示す。Figure 1 (al is a schematic perspective view of an embodiment of the present invention, Figure 1 (
b), (C1 is the energy level and electron gas of the channel region 5 on the cross section XX' and the channel regions 58 and 5B on the cross section YY' for the case where the control voltage vG is not applied and when it is applied, respectively. 4 distribution is shown.
図において、1は半絶縁性GaAs基板、2はノンドー
プのi型GaAs層、3は例えばシリコン(Si)を濃
度2X10”cm−3程度にドープしたn型AlXGa
、−。In the figure, 1 is a semi-insulating GaAs substrate, 2 is an undoped i-type GaAs layer, and 3 is an n-type AlXGa layer doped with silicon (Si) to a concentration of about 2X10"cm-3.
,-.
As (x −0,3)電子供給層、4は準1次元電子
ガス、5.5A、5Bはチャネル領域、6.7A、7B
は例えばAuGe/Auからなるオーミックコンタクト
電極、8八、8Bは後述する制御電極、9は抵抗体であ
る。As (x -0,3) electron supply layer, 4 is quasi-one-dimensional electron gas, 5.5A, 5B are channel regions, 6.7A, 7B
is an ohmic contact electrode made of, for example, AuGe/Au, 88 and 8B are control electrodes to be described later, and 9 is a resistor.
本実施例は例えば下記の様に製造される。This example is manufactured, for example, as follows.
半絶縁性GaAs基板1上に例えば分子線エピタキシャ
ル成長方法により、ノンドープのi型GaAs層2を厚
さ例えば0.5〜1μmに、n型AlxGa+−xAs
電子供給層3を厚さ例えば40〜50nm程度にエピタ
キシャル成長する。この半導体基体をメサエッチングし
て、幅例えば0.1μm程度のストライプ状のチャネル
領域5と、これが分岐して幅が例えばそれぞれ0.II
!m程度のチャネル領域5A、5Bをパターニングする
。A non-doped i-type GaAs layer 2 is formed on a semi-insulating GaAs substrate 1 to a thickness of, for example, 0.5 to 1 μm by, for example, a molecular beam epitaxial growth method, and is made of n-type AlxGa+-xAs.
The electron supply layer 3 is epitaxially grown to a thickness of, for example, about 40 to 50 nm. This semiconductor substrate is mesa-etched to form a striped channel region 5 having a width of, for example, about 0.1 μm, and a striped channel region 5 having a width of, for example, about 0.1 μm. II
! Channel regions 5A and 5B of about m are patterned.
このチャネル領域5.5八、5Bの端部に、例えばSi
をエネルギー100keV程度でドーズ量I XIOI
ffcmぺ程度イオン注入し、活性化熱処理を行ってn
型オーミックコンタクト領域(図示を省略)を形成し、
例えば八uGe/Auからなるオーミックコンタクト電
極6、ハ、7Bを配設して合金化熱処理を行う。At the end of this channel region 5.58, 5B, for example, Si
with an energy of about 100 keV and a dose of I
After ion implantation to a degree of ffcm and activation heat treatment,
forming a type ohmic contact region (not shown);
For example, ohmic contact electrodes 6, 7B made of Ge/Au are provided and alloying heat treatment is performed.
チャネル領域5が5A、5Bに分岐する位置の近傍に制
御電極8A、8Bを、i型GaAs層2との間にショッ
トキバリアが形成される電極材料例えばアルミニウム(
AI)を用いて形成する。この電極の一方例えば電極8
Aはチャネル領域の電位をオーミックコンタクト電極
6等に対して一定に保持するために用い、他方の電極8
Bは電極8Aとの間の電位差によって前記の制御を行う
。Control electrodes 8A and 8B are placed near the positions where the channel region 5 branches into 5A and 5B using an electrode material, such as aluminum (
AI). One of these electrodes, for example electrode 8
A is used to keep the potential of the channel region constant with respect to the ohmic contact electrode 6, etc., and the other electrode 8
B performs the above control based on the potential difference between electrode 8A and electrode 8A.
また抵抗体9は、例えばタングステンシリサイド(WS
iX)を窒素(N2)を添加したアルゴン(Ar)ガス
中でスパッタし、バターニングしている。Further, the resistor 9 is made of, for example, tungsten silicide (WS).
iX) was sputtered and patterned in argon (Ar) gas to which nitrogen (N2) was added.
本実施例の等価回路は第2図の様に表され、6.7A、
7B、8Bは各電極に対応し、R1は抵抗体9、R1、
R5A% l’lsI!は各チャネル領域の抵抗を表す
。ただしR5、R5A、R2Hはほぼ等しく、R1はこ
れらより大きいものとする。The equivalent circuit of this example is shown in Figure 2, with 6.7A,
7B and 8B correspond to each electrode, R1 is a resistor 9, R1,
R5A% l'lsI! represents the resistance of each channel region. However, R5, R5A, and R2H are approximately equal, and R1 is larger than these.
本実施例の電極6を接地しくVs=O)電極7Aに電圧
V、Jを与えて、電極7Bの電圧を出力■。とじて取り
出す場合に、電極8B −8A間の電圧vG−0のとき
にはチャネル領域5A、5B双方に電流が通じて、■。By grounding the electrode 6 of this embodiment, voltages V and J are applied to the electrode 7A (Vs=O), and the voltage of the electrode 7B is output. When the voltage between the electrodes 8B and 8A is vG-0, current flows through both the channel regions 5A and 5B.
#0 となる。他方電極8Bに電極8Aに対して負の電
圧VGを与えてチャネル領域5Bの電流を遮断すればV
。−■。となり、スイッチング動作が行われる。It becomes #0. If a negative voltage VG is applied to the other electrode 8B with respect to the electrode 8A to interrupt the current in the channel region 5B, V
. −■. Therefore, a switching operation is performed.
本実施例では例えば温度77Kにおいて電子移動度が約
I X 10”cm2/V、s テあり、従来ノHEM
Tニよる同等の回路より更に高速のスイッチング動作が
実現されている。In this embodiment, for example, the electron mobility at a temperature of 77K is approximately I
A faster switching operation is realized than an equivalent circuit based on T2.
前記実施例等ではGaAs系半導体基体を用い、電子を
キャリアとしているが、半導体材料はGaAs /Al
GaAs系に■られず、例えばInGaAs / In
AlAs系等の半導体基体にも同様に適用でき、またキ
ャリアを正札とした場合にもその2次元状態に比較して
温かに高速の動作を実現することができる。In the above embodiments, a GaAs-based semiconductor substrate is used and electrons are used as carriers, but the semiconductor material is GaAs/Al.
For example, InGaAs/In
It can be similarly applied to semiconductor substrates such as AlAs-based, and even when the carrier is used as a genuine bill, warmer and faster operation can be realized compared to its two-dimensional state.
以上説明した如く本発明によれば、1次元に準する量子
化状態のキャリアの伝導路を制御することにより、半導
体装置の高速化が極めて高い移動度により一層推進され
、例えば次世代の電子計算システム等に大きい効果を与
える。As explained above, according to the present invention, by controlling the conduction path of carriers in a quantized state quasi-one-dimensional, the speed-up of semiconductor devices is further promoted by extremely high mobility, and, for example, next-generation electronic calculation It has a great effect on the system etc.
第1図(a)は本発明の実施例の模式斜視図、第1図(
bl、(C)はそのチャネルのエネルギー準位及び電子
ガスの分布を示す図、
第2図は実施例の等価回路図、
第3図は従来のHEMTの模式側断面図である。
図において、
1は半絶縁性GaAs基板、
2はノンドープのi型GaAs層、
3はn型AlxGa+−xAs層、
4は電子ガス、
5.5A、 5Bはチャネル領域1.
6.7はオーミックコンタクト電極、
8A、 8Bは制御電極、
9は抵抗体を示す。FIG. 1(a) is a schematic perspective view of an embodiment of the present invention, FIG.
FIG. 2 is an equivalent circuit diagram of the embodiment, and FIG. 3 is a schematic side sectional view of a conventional HEMT. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a non-doped i-type GaAs layer, 3 is an n-type AlxGa+-xAs layer, 4 is an electron gas, 5.5A and 5B are channel regions 1. 6.7 is an ohmic contact electrode, 8A and 8B are control electrodes, and 9 is a resistor.
Claims (1)
イプ状の領域が設けられて、少なくとも該界面に垂直方
向について量子化されたキャリアが該領域内に生成され
、 該領域の分岐点近傍に設けられた電極により該キャリア
の該界面に平行方向の分布を制御して、該キャリアの伝
導路を選択することを特徴とする半導体装置。[Claims] A striped region parallel to and including the heterojunction interface of the semiconductor layer is provided, and carriers quantized at least in a direction perpendicular to the interface are generated in the region, the region A semiconductor device characterized in that a conduction path of the carriers is selected by controlling the distribution of the carriers in a direction parallel to the interface by an electrode provided near a branch point of the carriers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5070887A JPS63216379A (en) | 1987-03-05 | 1987-03-05 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5070887A JPS63216379A (en) | 1987-03-05 | 1987-03-05 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63216379A true JPS63216379A (en) | 1988-09-08 |
Family
ID=12866397
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5070887A Pending JPS63216379A (en) | 1987-03-05 | 1987-03-05 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63216379A (en) |
-
1987
- 1987-03-05 JP JP5070887A patent/JPS63216379A/en active Pending
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