JPS6373670A - Conductive modulation type mosfet - Google Patents
Conductive modulation type mosfetInfo
- Publication number
- JPS6373670A JPS6373670A JP21843286A JP21843286A JPS6373670A JP S6373670 A JPS6373670 A JP S6373670A JP 21843286 A JP21843286 A JP 21843286A JP 21843286 A JP21843286 A JP 21843286A JP S6373670 A JPS6373670 A JP S6373670A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- width
- gate electrode
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 230000000737 periodic effect Effects 0.000 claims description 3
- 230000000630 rising effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000001066 destructive effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- -1 Phosphorus ions Chemical class 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Abstract
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、導電変調型ＭＯ３ＦＥＴに関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a conductivity modulated MO3FET.
（従来の技術）
近年、電力用スイッチング素子として、Ｄ Ｓ Ａ （
Ｄ １Ｈｕｓｉｏｎ Ｓ ｅｌｆ Ａ Ｉｉｎｇｎ
）法によりソースおよびチャネル領域を形成するパワ
ーＭＯ３ＦＥＴが市場に現れている。しこしこの素子は
１０００Ｖ以上の高耐圧ではオン抵抗が高くなってしま
い、大Ｎ流を流すことが難しい。これに代わる有力な素
子として、ドレイン領域にソースとは逆の導電型層を設
けることにより、高抵抗層に導電変調を起こさせてオン
抵抗を下げるようにした、いわゆる導電変調型ＭＯＳＦ
ＥＴが知られている。導電変調型ＭＯ３ＦＥＴは一般に
次のように形成される。ドレイン層となるｐ４″Ｓｉ基
板にｎ＋型バッファ層を介してｎ−型高抵抗層が形成さ
れる。この高抵抗層上にゲート絶縁膜を介してストライ
ブ状の開口を有するゲート電極が形成され、このゲート
電極をマスクとして不純物の二重拡散を行うことにより
、ｐ型ベース層とその端部に自己整合されたｎ型ソース
層が形成される。(Prior art) In recent years, DSA (
D 1 Fusion S elf A Iingn
) power MO3FETs whose source and channel regions are formed by the method have appeared on the market. This stiff element has a high on-resistance at a high breakdown voltage of 1000 V or more, making it difficult to pass a large N current. A promising alternative element is a so-called conductivity modulation type MOSF, which lowers the on-resistance by causing conductivity modulation in the high-resistance layer by providing a layer of conductivity type opposite to that of the source in the drain region.
ET is known. A conductivity modulated MO3FET is generally formed as follows. An n-type high-resistance layer is formed on a p4'' Si substrate that will serve as a drain layer via an n+-type buffer layer.A gate electrode having a striped opening is formed on this high-resistance layer via a gate insulating film. By performing double diffusion of impurities using this gate electrode as a mask, a p-type base layer and an n-type source layer self-aligned at the end thereof are formed.
これにより、ゲート電橿下のｎ型ソース層とｎ−型高抵
抗層で挟まれたｐ型ベース層表面にチャネルｍ域が形成
される。ソース層とベース層には双方にコンタクトする
ソース電極が形成され、ドレイン層にはドレインＩＩＩ
が形成される。As a result, a channel m region is formed on the surface of the p-type base layer sandwiched between the n-type source layer and the n-type high-resistance layer under the gate electrode. A source electrode in contact with both the source layer and the base layer is formed, and a drain III is formed in the drain layer.
is formed.
この導電変調型ＭＯＳＦＥＴでは、ゲート電極に正電圧
を印加してターンオンする際、ｎ＋＋ソース層からチャ
ネル領域を通ってｎ−型高抵抗層に注入される電子電流
に対して、ｐ＋型トド１４２層ら正孔注入が起り、この
結果ｎ−型高抵抗層には多量のキャリア蓄積による導電
変調が起こる。In this conductivity modulation type MOSFET, when a positive voltage is applied to the gate electrode to turn it on, the p+ type TODO 142 layer resists the electron current injected from the n++ source layer through the channel region to the n- type high resistance layer. As a result, conductivity modulation occurs in the n-type high resistance layer due to the accumulation of a large amount of carriers.
ｎ−型高抵抗層に注入された正孔電流は、ｎ１型ソ一ス
層下のｐ型ベース層を通り、ソース電極にぬける。ソー
ス電極はｎ１型ソ一ス層とｐ型ベース層を短絡している
ため、サイリスタ動作は阻止される。ゲート・ソース間
電圧を零とすれば、素子はターンオフする。The hole current injected into the n-type high resistance layer passes through the p-type base layer under the n1-type source layer and into the source electrode. Since the source electrode short-circuits the n1 type source layer and the p type base layer, thyristor operation is prevented. When the gate-source voltage is zero, the device is turned off.
この導電変調型ＭＯＳＦＥＴは、高耐圧化した場合にも
、従来のパワーＭＯＳＦＥＴに比べて導電変調の結果と
して十分に低いオン電圧が１ｑられる。Even when the withstand voltage is increased, this conductive modulation type MOSFET has a sufficiently lower on-voltage of 1q as a result of conductive modulation compared to a conventional power MOSFET.
しかしながらこの導電変調型ＭＯＳＦＥＴにも未だ問題
がある。第１に、素子を流れる電流の密度が大きくなる
と、ソース層下の横方向抵抗による電圧降下が大きくな
る。そしてｐ型ベース層とｎ＋型リソース層間順バイア
スされるようになるとサイリスタ動作に入り、ゲート・
ソース間バイアスを零にしても素子がオフしない、いわ
ゆるラッチアップ現象が生じる。この問題を解決する方
法として従来、ｐ型ベース層を深く拡散する方法、ｐ型
ベース層内に重ねて深くｐ型層を拡散する方法等が採用
されている。しかしこれらの方法では、オン電圧の上昇
を招く。第６図はその様子を示すもので、ｐ型ベース層
の拡散深さＸｐとオン電圧ＶＦおよびラッチアップ電流
ＩＬの関係を示す。However, this conductivity modulation type MOSFET still has problems. First, as the density of current flowing through the device increases, the voltage drop due to the lateral resistance under the source layer increases. Then, when the p-type base layer and the n+ type resource layer become forward biased, the thyristor operation begins, and the gate and
A so-called latch-up phenomenon occurs in which the device does not turn off even if the source-to-source bias is reduced to zero. Conventionally, methods for solving this problem include a method of deeply diffusing a p-type base layer, a method of deeply diffusing a p-type layer overlaid within a p-type base layer, and the like. However, these methods lead to an increase in on-state voltage. FIG. 6 shows this situation, and shows the relationship between the diffusion depth Xp of the p-type base layer, the on-voltage VF, and the latch-up current IL.
オン電圧を低くするには、ｐ型ベース層の拡散深さＸｐ
は浅くしなければならないが、これによりラッチアップ
電流ＩＬは小さくなる。第２に、従来の導電変調型ＭＯ
３ＦＥＴでは負荷短絡耐量がまだ不十分である。導電変
調型ＭＯ３ＦＥＴをインバータ装置等に用いて負荷が短
絡した場合、ドレイン・ソース間には電源電圧電圧がそ
のままかかり過大な電流が流れるために、この状態が続
くと導電変調型ＭＯ５ＦＥＴは破壊される。これを防止
するためには保護回路が用いられるが、負荷短絡が発生
してから保護回路が作動するまでの概略１０μｓｅｃの
時間破壊しない耐量を有することが要求される。これが
負荷短絡耐量である。素子の順方向阻止電圧が高くなる
と数機い電圧も高くなり、負荷短絡耐量も大きくしなけ
ればならない。In order to lower the on-voltage, the diffusion depth of the p-type base layer
must be made shallow, which reduces the latch-up current IL. Second, conventional conduction modulation type MO
3FET still has insufficient load short-circuit capability. If a conduction modulation type MO3FET is used in an inverter device or the like and the load is short-circuited, the power supply voltage will be applied between the drain and source and an excessive current will flow, so if this condition continues, the conduction modulation type MO5FET will be destroyed. . In order to prevent this, a protection circuit is used, but it is required that the protection circuit has the ability to withstand breakdown for approximately 10 μsec from the occurrence of a load short circuit to the activation of the protection circuit. This is the load short-circuit tolerance. As the forward blocking voltage of the element increases, the voltage also increases by several orders of magnitude, and the load short-circuit resistance must also be increased.
（発明が解決しようとする問題点）
以上のように従来の導電変調型ＭＯＳＦＥＴは、オン電
圧を上昇させることなくラッチアップ電流の大幅な増大
を図ることが難しく、負荷短絡耐量が不十分である、と
いう問題があった。(Problems to be Solved by the Invention) As described above, in the conventional conduction modulation type MOSFET, it is difficult to significantly increase the latch-up current without increasing the on-state voltage, and the load short-circuit resistance is insufficient. There was a problem.
本発明はこ′の様な問題を解決した導電変調型ＭＯＳＦ
ＥＴを提供することを目的とする。The present invention is a conductive modulation type MOSF that solves these problems.
The purpose is to provide ET.
［発明の構成コ
（問題点を解決するための手段）
本発明にかかる導電変調型ＭＯ３ＦＥＴは、第１導電型
ドレイン層上に第２導電型の低抵抗バッファ層を介して
第２導電型の高抵抗層を有し、この高抵抗層上にゲート
絶縁膜を介して格子状のゲート電極が配設され、このゲ
ート電極の開口部からの不純物拡散により第１導電型ベ
ース層およびこのベース層内に位置する第２導電型ソー
ス層が形成され、かつソース領域は不連続的に形成され
てＭＯＳＦＥＴ動作をする実効的チャネル領域とＭＯＳ
ＦＥＴ動作をしない領域が周期的に形成され、ドレイン
層にコンタクトするドレイン電極、およびソース層とベ
ース層に同時にコンタクトするソース電極を有する。こ
の様な導電変調型Ｍ ＯＳ Ｆ Ｅ Ｔにおいて、本発
明は、ゲート電極の幅をＬａｓベース層とドレイン層に
挟まれる高抵抗層の幅をＷｎとしたとき、
Ｌｏ≧３０μｍ
Ｗｎ≧１２０μｍ
なる条件を満たすようにしたことを特徴とする。[Configuration of the Invention (Means for Solving Problems)] The conductivity modulation type MO3FET according to the present invention has a conductivity modulation type MO3FET in which a second conductivity type is formed on a first conductivity type drain layer via a second conductivity type low resistance buffer layer. A lattice-shaped gate electrode is disposed on the high-resistance layer via a gate insulating film, and impurities are diffused from the opening of the gate electrode to form a first conductivity type base layer and this base layer. A source layer of a second conductivity type located within is formed, and the source region is formed discontinuously to form an effective channel region and a MOS for MOSFET operation.
Regions that do not perform FET operation are periodically formed and have a drain electrode in contact with the drain layer and a source electrode in contact with the source layer and the base layer at the same time. In such a conductivity modulation type MOS FET, the present invention provides the following conditions: Lo≧30μm Wn≧120μm, where the width of the gate electrode is Las and the width of the high resistance layer sandwiched between the base layer and the drain layer is Wn. It is characterized by satisfying the following.
（作用）
上述のような設計パラメータを限定することにより、後
に具体的なデータを挙げて説明するように導電変調型Ｍ
Ｏ３ＦＥＴの特性の大幅な改善が図られる。即ち、ゲー
ト電極幅Ｌｏを大きくすることにより、オン電圧を上昇
させることなくラッチアップ電流の増大を図ることがで
き、また高抵抗層幅Ｗｎを大きく設定することにより負
荷短絡耐量の改善を図ることができる。(Function) By limiting the design parameters as described above, conductive modulation type M
Significant improvement in the characteristics of O3FET is achieved. That is, by increasing the gate electrode width Lo, it is possible to increase the latch-up current without increasing the on-voltage, and by setting the high resistance layer width Wn large, it is possible to improve the load short circuit withstand capability. Can be done.
（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
第１図（ａ）（ｂ）は一実施例の導電変調型ＭＯＳＦＥ
Ｔを示す平面図とそのＡ−Ａ’断面図である。１１はｐ
＋型ドレイン層１１であり、この上にｎ＋型バッファ１
１２を介してｎ−型高抵抗ｌ！！１３が形成されている
。この高抵抗層１３上にゲート絶縁ｌ１１１４を介して
例えば多結晶シリコン膜によりゲート電極１５が形成さ
れている。ゲート電極１５は第１図（ａ）に斜線を施し
て示したように、ストライプ状の間隙（開口部）１６を
有する格子状に配設形成される。このゲート電極１５を
マスクとしてＤＳＡ法による不純物拡散を行うことによ
り、ｐ型ベース層１７およびｎ＋型ソース層１８が形成
されている。ソース層１８は第１図（ａ）に示すように
不連続的に配列形成される。これにより、ｐ型ベース層
の端部、即ちソース層１８と高抵抗層１３に挟まれた領
域のｐ型ベース層１７表面にチャネル領域１９が形成さ
れる。チャネル領域１９は、実際にＭＯ３ＦＥＴ動作を
する実効チャネル領域１９ａと、ソース層がない部分の
ＭＯＳＦＥＴ動作をしない領域１９ｂとが周期的に配列
形成された状態になる。２０はソース層１８とベース層
１７に同時にコンタクトするソース電極であり、２１は
ドレイン電極である。ｐ型ベース層１７の中央部には、
その横方向抵抗を小さくするためにｐ＋型！２２が拡散
形成されている。Figures 1(a) and 1(b) show an example of a conductivity modulation type MOSFE.
It is a top view which shows T, and its AA' sectional view. 11 is p
+ type drain layer 11, and an n+ type buffer 1 on top of this.
12 through n-type high resistance l! ! 13 are formed. A gate electrode 15 made of, for example, a polycrystalline silicon film is formed on this high resistance layer 13 via a gate insulator 1114. The gate electrode 15 is arranged in a lattice shape having striped gaps (openings) 16, as shown by hatching in FIG. 1(a). A p-type base layer 17 and an n+-type source layer 18 are formed by performing impurity diffusion using the DSA method using this gate electrode 15 as a mask. The source layers 18 are discontinuously arranged as shown in FIG. 1(a). As a result, a channel region 19 is formed at the end of the p-type base layer, that is, on the surface of the p-type base layer 17 in a region sandwiched between the source layer 18 and the high-resistance layer 13. In the channel region 19, an effective channel region 19a that actually performs MO3FET operation and a region 19b that does not perform MOSFET operation where there is no source layer are arranged in a periodic manner. 20 is a source electrode that contacts the source layer 18 and base layer 17 at the same time, and 21 is a drain electrode. In the center of the p-type base layer 17,
P+ type to reduce the lateral resistance! 22 is formed by diffusion.
この様な構成においてこの実施例では、ゲート電極幅Ｌ
ｏを３０μｍ以上に設定し、またｐ型ベース層１７とド
レイン層１１の間（より正確には、ｐ＋型層２２とｎ”
型バフフッ層１２の間）の＾抵抗層１３の幅Ｗｎを１２
０μｍ以上に設定する。In this embodiment, in such a configuration, the gate electrode width L
o is set to 30 μm or more, and between the p-type base layer 17 and the drain layer 11 (more precisely, between the p+ type layer 22 and n”
The width Wn of the resistance layer 13 (between the mold buffing layers 12) is 12
Set to 0 μm or more.
この素子の具体的な製造工程例を説明すると、次の通り
である。先ず０．００１〜０．００４Ω” ａｒｔのρ
１型Ｓｉ基板と、１００〜１５０Ω”／Ｊのｎ゛型Ｓｉ
基板を用意する。ｎ−型Ｓ１基板の一方の鏡面研磨面に
ドーズ１０．５〜１×１０１８／α２のリン・イオン注
入を行い熱処理する。次にｐ＋型Ｓｉ基板の鏡面研磨面
とｎ−型３ｉ基板のリン・イオン注入面を、直接接着技
術により接合させる。これにより、ｐ型ドレイン層１１
−ｎ＋型バッファ層１２−ｎ−型高抵抗層１３のウェー
ハが得られる。ここでｎ−型Ｓｉ基板の厚さは、最終的
に高抵抗層１３の幅Ｗｎが１２０μｍ以上となるように
予め調整しておく。A specific example of the manufacturing process for this element will be explained as follows. First, ρ of 0.001~0.004Ω” art
1-type Si substrate and 100-150Ω”/J n-type Si substrate
Prepare the board. Phosphorus ions are implanted at a dose of 10.5 to 1.times.10@18 /.alpha.2 into one mirror-polished surface of the n-type S1 substrate, followed by heat treatment. Next, the mirror polished surface of the p+ type Si substrate and the phosphorus ion implanted surface of the n− type 3i substrate are bonded together by direct bonding technology. As a result, the p-type drain layer 11
A wafer of -n+ type buffer layer 12-n- type high resistance layer 13 is obtained. Here, the thickness of the n-type Si substrate is adjusted in advance so that the final width Wn of the high resistance layer 13 is 120 μm or more.
この後ｎ−型高抵抗１１１３表面にゲート絶縁膜１４と
して１０００人の熱酸化膜を形成し、この上に５０００
人の多結晶シリコン膜を堆積する。After this, a thermal oxide film of 1,000 layers is formed on the surface of the n-type high resistance layer 1113 as the gate insulating film 14, and on this
Deposit a polycrystalline silicon film.
そしてこの多結晶シリコン膜を、周期的な開口部１６を
有するようにエツチング加工してゲート電極１５とする
。ゲート電極１５の幅Ｌｏは３０μｍ以上とする。次に
このゲート電極１４をマスクとしてボロンを拡散してｐ
型ベース層１７を形成する。更にゲート電極１５をマス
クの一部として用いて、ヒ素をドーズ１５Ｘ１０Ｉｓ／
、、２イオン注入して熱処理し、ソース層１８を形成す
る。This polycrystalline silicon film is then etched to form a gate electrode 15 so as to have periodic openings 16. The width Lo of the gate electrode 15 is set to be 30 μm or more. Next, using this gate electrode 14 as a mask, boron is diffused and p
A mold base layer 17 is formed. Furthermore, using the gate electrode 15 as part of a mask, arsenic is applied at a dose of 15×10 Is/
, 2 ions are implanted and heat treated to form the source layer 18.
ソースＷＪ１８は第１図（ａ）に示すように不連続的に
複数個配列される。この後全面をＣＶＤＭ化躾で覆い、
これにコンタクト孔を開けてソース電極２０を形成する
。基板裏面には、Ｖ−Ｎｉ−Ａｕｉ！ｌの蒸着によりド
レイン電極２１を形成する。A plurality of source WJs 18 are arranged discontinuously as shown in FIG. 1(a). After this, the entire surface is covered with CVDM treatment,
A contact hole is opened in this to form a source electrode 20. On the back side of the board, V-Ni-Aui! A drain electrode 21 is formed by evaporating 1.
以上のようにして、ゲート′Ｒ極幅Ｌｏ≧３０μ肌、高
抵抗層幅Ｗ ｎ≧１２０μｍの導電変調型ＭＯ３ＦＥＴ
が得られる。またチャネル領域は、通常のＭＯＳＦＥＴ
動作をする実効的チャネル領域１９ａと、ソース層がな
いためにＭＯＳＦＥＴ動作しない領ＩＵ１９ｂが交互に
配列された状態となる。As described above, conduction modulation type MO3FET with gate 'R pole width Lo≧30μm and high resistance layer width Wn≧120μm
is obtained. Also, the channel region is a normal MOSFET.
The effective channel region 19a that operates and the region IU 19b that does not operate as a MOSFET because there is no source layer are arranged alternately.
この実施例の導電変調型ＭＯＳＦＥＴでは、素子がオン
のときにゲート電極１５下に開口するｎ−型層１３から
ｐ型ペース！１１７にドレインから注入される正孔電流
のうち、チャネル領域１９ｂを通るものはソース層１８
下を通らず直接ソース電極２０に流れる。即ちソース層
１８の間は正孔電流のバイパス領域となっており、ソー
ス層下の横方向抵抗が実効的に小さくなり、大電流まで
ラッチアップ現象を生じない。In the conductivity modulation type MOSFET of this embodiment, when the device is on, a p-type layer is formed from the n-type layer 13 which opens below the gate electrode 15. Of the hole current injected from the drain to the source layer 117, the one that passes through the channel region 19b flows through the source layer 18.
It flows directly to the source electrode 20 without passing under it. That is, the space between the source layers 18 serves as a bypass region for hole current, and the lateral resistance under the source layer is effectively reduced, so that latch-up does not occur even at large currents.
以上のような構造パラメータの設定により優れた素子特
性が得れる理由を、具体的な実験データに基づいて次に
説明する。前述したようにラッチアップ電流の増大を図
るために単にチャネル長βを大きくするだけでは、オン
電圧が急激に増大する。The reason why excellent device characteristics can be obtained by setting the structural parameters as described above will be explained below based on specific experimental data. As described above, if the channel length β is simply increased in order to increase the latch-up current, the on-state voltage will increase rapidly.
第２図は、ゲート電極幅Ｌｏとオン電圧ＶＦの関係を測
定した結果である。ｐ型ベース層拡散深さが４μｍで、
前述のようにバイパス領域を設けた素子では、オン電圧
ＶＦはゲートＮ極幅Ｌｏに大きく依存し、Ｌｏが３０μ
ｍ以上になると低いオン電圧が得られることが分る。FIG. 2 shows the results of measuring the relationship between the gate electrode width Lo and the on-voltage VF. The p-type base layer diffusion depth is 4 μm,
As mentioned above, in a device provided with a bypass region, the on-voltage VF largely depends on the gate N-pole width Lo, and when Lo is 30μ
It can be seen that a low on-voltage can be obtained when the value is m or more.
第３図はゲート電極幅Ｌｏとラッチアップ電流ＩＬの関
係を示す。第３図の縦軸はＬａ−２０μ而におけるラッ
チアップ電流を１とした時のラッチアップｉ！！流の変
化率である。図示のようにバイパス領域がない素子では
ラッチアップ電流は低く、またゲート電極幅Ｌｏが大き
くなるとラッチアップ電流は低下しているが、バイパス
領域Ａ域を設けた素子ではゲート電極幅Ｌｏが大きくな
ってもラッチアップ電流の低下は認められない。FIG. 3 shows the relationship between the gate electrode width Lo and the latch-up current IL. The vertical axis in Figure 3 is the latch-up i! when the latch-up current at La-20μ is 1! ! is the rate of change of flow. As shown in the figure, the latch-up current is low in a device without a bypass region, and the latch-up current decreases as the gate electrode width Lo increases, but in a device with a bypass region A region, the gate electrode width Lo increases. However, no decrease in latch-up current was observed.
以上を纒めると、ソース層を不連続的に形成しバイパス
領域を設けた構造の導電変調型ＭＯＳＦＥＴにおいて、
ゲート電極幅Ｌｏを３０μｍ以上に設定することにより
、オン電圧ＶＦを余り上昇させることなく、効果的にラ
ッチアップ電流の増大を図ることができる。To summarize the above, in a conductivity modulation type MOSFET with a structure in which the source layer is formed discontinuously and a bypass region is provided,
By setting the gate electrode width Lo to 30 μm or more, the latch-up current can be effectively increased without significantly increasing the on-voltage VF.
次に負荷短絡耐量について説明する。順方向阻止電圧が
１０００Ｖ以上の導電変調型
ＭＯ３ＦＥＴでは、取扱い電圧が５００Ｖ以上になる。Next, load short-circuit tolerance will be explained. A conduction modulation type MO3FET with a forward blocking voltage of 1000V or more has a handling voltage of 500V or more.
またゲート電圧は１５Ｖである。従って、電源電圧１０
００Ｖ、ゲート電圧１５Ｖの条件で負荷短絡通電をおこ
ない、１０μｓｅｃの間素子が非破壊であれば、負荷短
絡耐量は十分であるといえる。そこで種々の構造パラメ
ータについて実験を行った結果、負荷短絡耐量はベース
暦とドレイン層に挟まれる高抵抗層の幅Ｗｎに依存する
ことが明らかになった。第４図がそのデータであり、Ｗ
ｎと素子の非破壊率の関係をヒストグラムで表わしたも
のである。図から明らかなように、Ｗｎが１２０μｍ以
上になると非破壊率が急激に高くなり、負荷短絡耐量が
十分大きくなることが分る。Further, the gate voltage is 15V. Therefore, the power supply voltage 10
If the load short-circuit current is applied under the conditions of 00 V and gate voltage of 15 V, and the element is not destroyed for 10 μsec, it can be said that the load short-circuit tolerance is sufficient. As a result of conducting experiments on various structural parameters, it became clear that the load short-circuit withstand capability depends on the width Wn of the high-resistance layer sandwiched between the base layer and the drain layer. Figure 4 shows the data, W
This is a histogram representing the relationship between n and the non-destructive rate of the element. As is clear from the figure, when Wn becomes 120 μm or more, the non-destructive rate increases rapidly, and the load short-circuit resistance becomes sufficiently large.
なお、Ｗｎが同一のとき、低抵抗バラフッ層がある場合
とない場合とでは、ある場合の方が負荷短絡耐量が大き
いことが確認された。It was confirmed that when Wn is the same, the load short-circuit withstand capacity is greater in the case with and without the low-resistance barrier layer.
第５図（ａ）（ｂ）は他の実施例の導電変調型ＭＯＳＦ
ＥＴの平面図とそのＢ−Ｂ−断面図である。先の実施例
と対応する部分には同じ符号を付して詳細な説明は省略
する。この実施例ではソース層１８連続的に形成されて
いる。そしてｐ型ベース層１７内にｐ＋型層２２と共に
、ソース側エツジが凹凸パターンとなるｐ９型１ｉ１２
３を形成している。即ちｐ＋型層２３は、チャネル領域
に終端するエツジとソース層１８下に終端するエツジが
交互に現われるパターンとし、チャネル領域１９が、Ｍ
ＯＳＦＥＴ動作に寄与する実効的チャネル領Ｉｔ１１９
ａと、ＭＯＳＦＥＴ動作に寄与しない領域１９ｂが交互
に配列形成された状態とする。FIGS. 5(a) and 5(b) are conduction modulation type MOSFs of other embodiments.
It is a top view of ET and its BB sectional view. Portions corresponding to those in the previous embodiment are given the same reference numerals and detailed explanations will be omitted. In this embodiment, the source layer 18 is formed continuously. Then, in the p-type base layer 17, together with the p+-type layer 22, the p9 type 1i12 whose source side edge has a concavo-convex pattern is formed.
3 is formed. That is, the p+ type layer 23 has a pattern in which edges terminating in the channel region and edges terminating below the source layer 18 appear alternately, and the channel region 19
Effective channel area It119 contributing to OSFET operation
A and regions 19b that do not contribute to MOSFET operation are arranged alternately.
つまりこの実施例では、チャネル領域１９ｂは、そのし
きい値がチャネル領域１９ａでのそれに比べて高く設定
されている。That is, in this embodiment, the threshold value of channel region 19b is set higher than that of channel region 19a.
この実施例の素子では、ゲート電極１５にオン・ゲート
信号を与えた時、チャネル領域１９ａがＭＯＳＦＥＴ動
作によりオンし、チャネル領域１９ｂではオンしない。In the device of this embodiment, when an on-gate signal is applied to the gate electrode 15, the channel region 19a is turned on by MOSFET operation, but the channel region 19b is not turned on.
高抵抗層１３で導電変調が起こって大電流が流れるオン
状態では、高抵抗層１３からの電流がチャネル領域１９
ｂをも流れるが、チャネル領域１９ａに比べるとｐ”型
層がソース１１１８の全体に亙って形成されているため
、ソース層下の横方向抵抗が小さく、ここでの電圧降下
は小さい。即ちチャネル領域１９ｂにバイパス領域を用
いた構造と等価になる。In the on state where conductivity modulation occurs in the high resistance layer 13 and a large current flows, the current from the high resistance layer 13 flows into the channel region 19.
However, since the p'' type layer is formed over the entire source 1118 compared to the channel region 19a, the lateral resistance under the source layer is small, and the voltage drop there is small. This is equivalent to a structure in which a bypass region is used in the channel region 19b.
従ってこの実施例の構造でも、ゲート電極幅Ｌｏおよび
高抵抗層幅Ｗｎを先の実施例と同様の条件に設定するこ
とにより、ラッチアップを生じることなく、大電流を流
すことができ、低いオン電圧を得ることができる。Therefore, even in the structure of this example, by setting the gate electrode width Lo and the high resistance layer width Wn to the same conditions as in the previous example, a large current can flow without latch-up, and a low on-state voltage can be obtained.
なお本発明は上記実施例に限られるものではなく、その
趣旨を逸脱しない範囲で種々変形して実施することがで
きる。Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the spirit thereof.
［発明の効果］
以上述べたように本発明によれば、素子パラメータの最
適設計により、オン電圧の上昇をもたらすことなくラッ
チアップＮ流の増大を図ることができ、また負荷短絡耐
量の向上を図った導電変調型ＭＯＳＦＥＴを得ることが
できる。[Effects of the Invention] As described above, according to the present invention, by optimally designing element parameters, it is possible to increase the latch-up N current without increasing the on-voltage, and to improve the load short-circuit resistance. A conductivity modulation type MOSFET as intended can be obtained.
第１図（ａ）（ｂ）は本発明の一実薇例の導電変調型Ｍ
ＯＳＦＥＴを示す平面図とそのＡ−Ａ’断面図、第２図
はゲート電極幅Ｌｏとオン電圧Ｖ、の関係を示す図、第
３図は同じくゲート電極幅Ｌｏとラッチアップ電流ＩＬ
の関係を示す図、第４図は高抵抗層幅Ｗｎと素子の非破
壊率の関係を示す図、第５図（ａ）（ｂ）は他の実施例
の導電変調型ＭＯ３ＦＥＴの平面図とそのＢ−８′断面
図、第６図はｐ型ベース層の拡散深さとオン電圧ＶＦお
よびラッチアップ電流ＩＬの関係を示す図である。
１１・・・ｐ４″型ドレイン層、１２・・・ｎ＋型バッ
ファ層、１３・・・ｎ−型高抵抗層、１４・・・ゲート
絶縁層、１５・・・ゲート電極、１６・・・間隙（開口
部）、１７・・・ｐ型ベース層、１８・・・ｎ＋型ソー
ス層、１９ａ・・・実効チャネル領域、１９ｂ・・・Ｍ
ＯＳＦＥＴ動作しないチャネル領域、２ｏ・・・ソース
ＩＩ４極、２１・・・ドレイン電極、２２．２３・・・
ｐ＋型層。
出願人代理人 弁理士 鈴江武彦
第 １ 囚
富２図
ｐ欠イノぐス力
Ｗｎ （ｐｍ〕
第Ｓ図
為６ｒＪＡFIGS. 1(a) and 1(b) show a conductive modulation type M as an example of the present invention.
A plan view showing an OSFET and its AA' cross-sectional view, FIG. 2 is a diagram showing the relationship between gate electrode width Lo and on-voltage V, and FIG. 3 is a diagram showing the relationship between gate electrode width Lo and latch-up current IL.
FIG. 4 is a diagram showing the relationship between the high resistance layer width Wn and the non-destructive rate of the device, and FIGS. The B-8' sectional view of FIG. 6 is a diagram showing the relationship between the diffusion depth of the p-type base layer, the on-voltage VF, and the latch-up current IL. DESCRIPTION OF SYMBOLS 11... P4'' type drain layer, 12... N+ type buffer layer, 13... N- type high resistance layer, 14... Gate insulating layer, 15... Gate electrode, 16... Gap (opening), 17...p type base layer, 18...n+ type source layer, 19a... effective channel region, 19b...M
OSFET non-operating channel region, 2o...4 source II poles, 21...drain electrode, 22.23...
p+ type layer. Applicant's representative Patent attorney Takehiko Suzue No. 1 Prisoner of wealth 2 figure p lack of innovation Wn (pm) Part S figure 6rJA
Claims (1)
領域に前記高抵抗層より不純物濃度が高い第２導電型の
低抵抗バッファ層を有し、前記高抵抗層上にゲート絶縁
膜を介してゲート電極が配設され、このゲート電極の間
隙部からの不純物拡散により第１導電型ベース層および
このベース層内に位置する第２導電型ソース層が形成さ
れ、前記ドレイン層にコンタクトするドレイン電極、お
よび前記ベース層とソース層の双方にコンタクトするソ
ース電極を有し、かつ前記ゲート電極下のチャネル領域
がＭＯＳＦＥＴ動作をする実効チャネル領域とＭＯＳＦ
ＥＴ動作をしない領域の周期的配列として形成された導
電変調型ＭＯＳＦＥＴおいて、前記ゲート電極の幅をＬ
＿Ｇ、前記ドレイン層とベース層に挟まれる高抵抗層の
幅をＷｎとしたとき、 Ｌ＿Ｇ≧３０μｍ Ｗｎ≧１２０μｍ を満たすことを特徴とする導電変調型 ＭＯＳＦＥＴ。Claims: A low-resistance buffer layer of a second conductivity type having a higher impurity concentration than the high-resistance layer is provided in a region sandwiched between the drain layer of the first conductivity type and the high-resistance layer of the second conductivity type; A gate electrode is provided on the resistance layer via a gate insulating film, and a first conductivity type base layer and a second conductivity type source layer located within this base layer are formed by impurity diffusion from the gap between the gate electrodes. a drain electrode that contacts the drain layer, and a source electrode that contacts both the base layer and the source layer, and a channel region under the gate electrode that operates as a MOSFET;
In a conductivity modulation MOSFET formed as a periodic array of regions that do not perform ET operation, the width of the gate electrode is set to L.
A conductivity modulation type MOSFET, characterized in that L_G≧30 μm and Wn≧120 μm, where Wn is the width of the high resistance layer sandwiched between the drain layer and the base layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61218432A JP2513640B2 (en) | 1986-09-17 | 1986-09-17 | Conduction modulation type MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61218432A JP2513640B2 (en) | 1986-09-17 | 1986-09-17 | Conduction modulation type MOSFET |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7246195A Division JP2718911B2 (en) | 1995-09-25 | 1995-09-25 | Conduction modulation type MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6373670A true JPS6373670A (en) | 1988-04-04 |
| JP2513640B2 JP2513640B2 (en) | 1996-07-03 |
Family
ID=16719816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61218432A Expired - Lifetime JP2513640B2 (en) | 1986-09-17 | 1986-09-17 | Conduction modulation type MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2513640B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4990975A (en) * | 1988-12-16 | 1991-02-05 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor and method of manufacturing the same |
| JPH04133355A (en) * | 1990-09-25 | 1992-05-07 | Fuji Electric Co Ltd | Insulated gate type bipolar transistor |
| US5489788A (en) * | 1993-03-09 | 1996-02-06 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device with improved short-circuit tolerance |
| US5703383A (en) * | 1995-04-11 | 1997-12-30 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| JP2009289988A (en) * | 2008-05-29 | 2009-12-10 | Fuji Electric Device Technology Co Ltd | High-breakdown voltage vertical mosfet |
| CN106952945A (en) * | 2017-03-24 | 2017-07-14 | 深圳深爱半导体股份有限公司 | Power semiconductor and its manufacture method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS605568A (en) * | 1983-06-23 | 1985-01-12 | Sanken Electric Co Ltd | Vertical insulated gate field effect transistor |
| JPS6182477A (en) * | 1984-09-29 | 1986-04-26 | Toshiba Corp | Conduction modulation type mosfet |
| JPS61208268A (en) * | 1985-03-13 | 1986-09-16 | Toshiba Corp | Conductance modulation type semiconductor device |
-
1986
- 1986-09-17 JP JP61218432A patent/JP2513640B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS605568A (en) * | 1983-06-23 | 1985-01-12 | Sanken Electric Co Ltd | Vertical insulated gate field effect transistor |
| JPS6182477A (en) * | 1984-09-29 | 1986-04-26 | Toshiba Corp | Conduction modulation type mosfet |
| JPS61208268A (en) * | 1985-03-13 | 1986-09-16 | Toshiba Corp | Conductance modulation type semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4990975A (en) * | 1988-12-16 | 1991-02-05 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor and method of manufacturing the same |
| JPH04133355A (en) * | 1990-09-25 | 1992-05-07 | Fuji Electric Co Ltd | Insulated gate type bipolar transistor |
| US5489788A (en) * | 1993-03-09 | 1996-02-06 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device with improved short-circuit tolerance |
| US5703383A (en) * | 1995-04-11 | 1997-12-30 | Kabushiki Kaisha Toshiba | Power semiconductor device |
| JP2009289988A (en) * | 2008-05-29 | 2009-12-10 | Fuji Electric Device Technology Co Ltd | High-breakdown voltage vertical mosfet |
| CN106952945A (en) * | 2017-03-24 | 2017-07-14 | 深圳深爱半导体股份有限公司 | Power semiconductor and its manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2513640B2 (en) | 1996-07-03 |
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