JPS6370717U - - Google Patents
Info
- Publication number
- JPS6370717U JPS6370717U JP16527886U JP16527886U JPS6370717U JP S6370717 U JPS6370717 U JP S6370717U JP 16527886 U JP16527886 U JP 16527886U JP 16527886 U JP16527886 U JP 16527886U JP S6370717 U JPS6370717 U JP S6370717U
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- supplied
- signal
- resistor
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000005236 sound signal Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案のスイツチング回路の一実施例
回路図、第２図はその動作説明用電圧波形図、第
３図は音声信号増幅ＩＣの構成図、第４図及び第
５図はミユート電圧形成回路を具体的な回路素子
で構成して示す本考案のスイツチング回路図であ
る。
１０…スイツチング回路、１１…ミユート電圧
形成回路、１１ａ，１１ｂ…入力端子、１１ｃ…
出力端子、１２…音声信号増幅ＩＣ、１３…スピ
ーカ、Ｃ…コンデンサ、Ｄ…ダイオード、Ｉｎ１
，Ｉｎ２…電圧入力端子、Ｑ１，Ｑ２…トランジ
スタ、Ｒ１〜Ｒ４…抵抗器。
Fig. 1 is a circuit diagram of an embodiment of the switching circuit of the present invention, Fig. 2 is a voltage waveform diagram for explaining its operation, Fig. 3 is a configuration diagram of an audio signal amplification IC, and Figs. 4 and 5 are the mute voltage. FIG. 3 is a switching circuit diagram of the present invention showing a forming circuit configured with specific circuit elements; DESCRIPTION OF SYMBOLS 10...Switching circuit, 11...Mute voltage formation circuit, 11a, 11b...Input terminal, 11c...
Output terminal, 12... Audio signal amplification IC, 13... Speaker, C... Capacitor, D... Diode, In1
, In2...voltage input terminal, Q1 , Q2 ...transistor, R1 to R4 ...resistor.
補正 昭６２．１．２９
実用新案登録請求の範囲を次のように補正する
。Amendment January 29, 1982 The scope of claims for utility model registration is amended as follows.
【実用新案登録請求の範囲】
一方の入力端子からの信号が抵抗器を介して、
エミツタが接地されたトランジスタのコレクタに
、あるいはコレクタが抵抗器を介して接地された
トランジスタのエミツタに供給され、他方の入力
端子からの信号はこのトランジスタのベースに供
給されると共に、上記コレクタからの信号は出力
端子に供給されるミユート電圧形成回路と、
上記一方の入力端子に、電源切断時に電荷を供
給するコンデンサと、
上記他方の入力端子に、入電時に適正な電圧を
供給する抵抗回路とを具備し、電源切断時にのみ
上記出力端子より電圧を発生するよう構成したこ
とを特徴とするスイツチング回路。 [Claims for Utility Model Registration] When the signal from one input terminal passes through a resistor,
The emitter is supplied to the collector of a transistor whose emitter is grounded, or the emitter of a transistor whose collector is grounded via a resistor, and the signal from the other input terminal is supplied to the base of this transistor, and the signal from the collector is supplied to the emitter of a transistor whose emitter is grounded. The signal is supplied to the output terminal by a mute voltage forming circuit, to one of the input terminals, a capacitor that supplies charge when the power is turned off, and to the other input terminal, a resistor circuit that supplies an appropriate voltage when the power is turned on. A switching circuit comprising: a switching circuit configured to generate a voltage from the output terminal only when the power is turned off.
Claims (1)
エミツタが接地されたトランジスタのコレクタに
、あるいはコレクタが抵抗器を介して接地された
トランジスタのエミツタに供給され、他方の入力
端子からの信号はこのトランジスタのベースに供
給されると共に、上記コレクタからの信号は出力
端子に供給されるミユート電圧形成回路と、 上記一方の入力端子に、電源切断時に電荷を供
給するコンデンサと、上記他方の入力端子に、入
電時に適正な電圧を供給する抵抗回路とを具備し
、電源切断時にのみ上記出力端子より電圧を発生
するよう構成したことを特徴とするスイツチング
回路。共に、接続して構成した実用新案登録請求
の範囲第１項記載のスイツチング回路。[Claims for Utility Model Registration] When the signal from one input terminal passes through a resistor,
The emitter is supplied to the collector of a transistor whose emitter is grounded, or the emitter of a transistor whose collector is grounded via a resistor, and the signal from the other input terminal is supplied to the base of this transistor, and the signal from the collector is supplied to the emitter of a transistor whose emitter is grounded. A signal is supplied to the output terminal by a mute voltage forming circuit, a capacitor that supplies charge to one of the input terminals when the power is turned off, and a resistor circuit to the other input terminal that supplies an appropriate voltage when the power is turned on. A switching circuit comprising: a switching circuit configured to generate a voltage from the output terminal only when the power is turned off. 1. A switching circuit according to claim 1, which is constructed by connecting the two together.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16527886U JPS6370717U (en) | 1986-10-28 | 1986-10-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16527886U JPS6370717U (en) | 1986-10-28 | 1986-10-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6370717U true JPS6370717U (en) | 1988-05-12 |
Family
ID=31095173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16527886U Pending JPS6370717U (en) | 1986-10-28 | 1986-10-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6370717U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH044416U (en) * | 1990-04-26 | 1992-01-16 |
-
1986
- 1986-10-28 JP JP16527886U patent/JPS6370717U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH044416U (en) * | 1990-04-26 | 1992-01-16 |
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